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Requirements
- 2-10 years (with Btech) or 8 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. • 2-3 years of management experience leading/mentoring a small team of engineers • Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet. • Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
Nice to Have
- Experience leading System testing efforts for SERDES solutions. • Experience in PCIe/UCIe LTSSM states is a plus. • 1-2 years of experience in FPGA Design and Schematic design. • 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus. • Familiarity with Verilog RTL coding for FPGA, python,C/C++ • Good communication skills We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
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Specialisation
Open roles at Cadence Design Systems
150 positions
Job ID
/job/BANGALORE/Design-Engineer-I_R50382
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