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Nice to Have
- First experience with ATE platforms (e.g., Advantest 93K, Teradyne) Basic knowledge of DFT and functional test methodologies First experience with hardware design (loadboards, packages) Familiarity with semiconductor manufacturing processes Basic knowledge of digital, mixed-signal, or memory testing (CMOS, DRAM, SRAM) Soft Skills Good analytical and problem-solving abilities.
- Curious mindset and willingness to learn new technologies.
- Ability to work effectively in multicultural and cross-functional teams.
- Good communication and collaboration skills.
- Good level of English required.
- Location Valbonne (Sophia Antipolis), France.
- The role involves regular collaboration with engineering teams located in France, India, and the United States.
- We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
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Specialisation
Open roles at Cadence Design Systems
622 positions
Job ID
/job/VALBONNE-Sophia/Test-Engineer-II_R54681-1
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