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About This Role
- You will be responsible for the front end design and verification of design blocks for these cores.
- Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation.
- You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation.
- Familiarity with entire ASIC design and implementation flow. · Ability to work independently as well as part of a large team spanning multiple geographies. · Education: BS/MS in Electrical or Computer Engineering or equivalent · Experience: Requires 6+ years with MS or 8+ years with BS in ASIC design / implementation · Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure. · Requires proficiency with the following design tools / flows: · TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler · Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries · Understanding of liberty LIB models for timing · Formal verification (Synopsys Formality / Cadence Conformal) · Spyglass Lint · Power analysis of RTL and gate level netlists · Familiarity with DFT (design for test) and scan methodology · Version control (svn, git, etc) Additional Job Description: Compensation and Benefits The salary range for this position is $51.92 - 83.07 per hour.
- This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents.
- Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
- The company follows all applicable laws for Paid Family Leave and other leaves of absence.
- We will also consider qualified applicants with arrest and conviction records consistent with local law.
- If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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398 positions
Job ID
/job/USA-TX-Austin---River-Place-B7/R-D-Engineer-IC-Design-4_R024801
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