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About This Role
- Staff Layout Engineer ( Station in Singapore ) Job descriptions and the level of expertise: The descriptions are for layout engineers for our Library Group.
- Library Group is a part of Central Engineering Group.
- In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.
About This Role
- IC Layout Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout Schedule time-line & layout floor-planning Complete quality layout and verification within planned schedule (without supervision for experienced engineer) Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team Skill Set (Mem) Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
- Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
- Good experience in Floor-planning, hierarchy layout and chip integration.
- Experience in memory compiler will be a plus.
- Knowledge of Script Programming and SKILL Programming would be a plus.
- Able to lead or train a team of junior engineers Good knowledge of memory layout topology.
- Ability to lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
- Self-reliant, with the ability to work independently as well as in a team.
- Good leadership quality in project management.
- Re-location Must be available to re-locate to Singapore immediately.
- We will also consider qualified applicants with arrest and conviction records consistent with local law.
- If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Job ID
/job/China-Shanghai-Zhangjiang-Hi-Tech/Staff-Layout-Engineer_R026691
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