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What You'll Do
- Develop the specifications of a block or subsystem in alignment with the product goals, by working closely with system architects Translate the design specification to an optimal micro-architecture for digital blocks Mentor and guide junior engineers to own parts of a subsystem RTL coding using Verilog and SystemVerilog Meet power, performance and area goals by micro-architecture optimization Block level Designer verification Work closely with DV team to develop test-plans Front end implementation – Lint/CDC , synthesis, Timing constraint development Work closely with DFT and PD teams for signoff Support Silicon validation Position requirements BE/BS/Mtech/M.E/PhD degree in Electrical/Electronics/Computer science from a reputed institute 6-15 years of relevant experience Block or subsystem design ownership experience for at least 3 years In depth understanding of digital logic design principles - control intensive, data-path intensive and multi domain clocking Strong hands-on RTL coding experience and debugging skills Digital Subsystem, clocking and full chip integration experience Expertise in timing constraints development and critical path timing closure Very good Experience in Synthesis and LEC Knowledge of industry standard bus protocols such as AHB, APB, AXI Experience in digital signal processing and Matlab modeling is highly desirable Experience in Processor subsystem design is highly desirable Excellent verbal and written communication skills to work effectively with teams spread geographically Experience in mentoring junior engineers Silicon debug and Product Evaluation , DFT support experience For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
- Department of Commerce - Bureau of Industry and Security and/or the U.S.
- Department of State - Directorate of Defense Trade Controls.
- As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
- We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
- Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days
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Salary range
₹5-12 LPA to ₹40-70 LPA
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/job/India-Bangalore-Nova/Staff-Digital-Design-Engineer_R252414
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