Top 30 Static Timing Analysis (STA) Interview Questions & Answers (India 2026)

TL;DR. STA rounds at Indian semiconductor companies test three things: whether you can compute setup and hold slack by hand from arrival and required times, whether you understand variation — OCV, derates, CRPR — well enough to defend a signoff number, and whether you have actually read a PrimeTime report on a real block. Product-company PD loops at Qualcomm, Intel and NVIDIA give timing its own 60-90 minute round, and that round sets your offer level more than any other. The 30 questions below — fundamentals to tool-specific — are the ones that actually come up, with the answers interviewers are listening for.

I have run timing-focused interview rounds for 8 years across Intel and Cadence — over 200 candidates. The pattern never changes: candidates recite the setup equation, then collapse the moment I add a second clock, a derate, or a multicycle exception. This is the companion deep-dive to my physical design interview guide; that post covers the full PD loop, this one goes all-in on the timing round. Roughly a third of the physical design openings on our job board call out STA or timing closure explicitly in the JD.

What STA interviewers actually measure

1. Hand calculation (30%). Compute slack on a whiteboard from a clock period, latencies, cell delays and library numbers. No tool to hide behind.
2. Variation and pessimism (30%). OCV, AOCV, POCV, derates, CRPR, uncertainty — this is where the 12 LPA and 35 LPA candidates diverge.
3. Exceptions and intent (20%). False paths, multicycle paths, max/min delay — can you write constraints that match design intent?
4. Tool fluency (20%). PrimeTime or Tempus: read a report top to bottom and say where the picoseconds went.

Fundamentals: questions 1-10

Every round opens here. Get these wrong and the interview is effectively over in fifteen minutes.

1. What is STA, and why is it preferred over dynamic timing simulation?
STA verifies every timing path against constraints without simulation vectors, computing worst-case and best-case delays from library models and extracted parasitics, then reporting slack. Dynamic simulation only checks the paths your vectors happen to exercise; STA is exhaustive and orders of magnitude faster. Its blind spot: it trusts your constraints completely — a wrong false path hides a real silicon bug.

2. Define setup and hold time. What physically happens on a violation?
Setup time is the window before the active clock edge in which data must be stable; hold time is the window after. Violate either and the flop can go metastable — output hovering at an intermediate voltage for an unbounded time before resolving unpredictably. Setup failures are frequency-dependent: slow the clock and they disappear. Hold failures are frequency-independent: the chip is dead at any speed. Say that last sentence unprompted and the interviewer relaxes.

3. Explain arrival time, required time, and slack.
Arrival time is when data actually reaches the endpoint: launch clock latency plus clock-to-Q plus combinational delay. Required time is when it is allowed to arrive — for setup, capture edge plus capture latency minus uncertainty minus library setup; hold is the mirror. Setup slack = required − arrival; hold slack = arrival − required; negative means violation.

4. What is clock skew, and how does it affect setup and hold?
Skew is capture clock arrival minus launch clock arrival. Positive skew (capture arrives later) adds effective cycle time for setup but hurts hold, because data races a delayed same-edge capture. Negative skew is the opposite. The follow-up is "so is positive skew good?" No — skew is a per-path property; what helps one path hurts the reverse path between the same flops.

5. Differentiate clock latency, skew, jitter, and uncertainty.
Latency is total insertion delay: source (clock origin to definition point) plus network (definition point to sink). Skew is the static spatial difference in arrival between sinks. Jitter is cycle-to-cycle variation of the clock edge itself, from PLL and supply noise. Uncertainty is an SDC knob (set_clock_uncertainty): pre-CTS it lumps expected skew, jitter and margin; post-CTS it should shrink to jitter plus margin, because skew is now a real propagated number.

6. Why is a hold violation more dangerous than a setup violation?
You cannot fix it in silicon by slowing the clock or binning to a lower speed grade — the part fails at every frequency. Hold is checked at the fast corner (FF process, high voltage), where data races hardest. One true hold violation on a functional path means dead silicon.

7. What are the four categories of timing paths?
Register-to-register, input-to-register, register-to-output, and input-to-output — plus clock-gating checks and recovery/removal for async controls. Each needs its own constraint coverage: create_clock handles reg2reg, input paths need set_input_delay with a reference clock, output paths need set_output_delay, and in2out needs both. Forgetting that in2out needs both delays is the common slip.

8. What are launch and capture edges?
The launch edge clocks data out of the start flop; the capture edge clocks it into the end flop. Default setup checks capture one cycle after launch; default hold checks that data launched on an edge does not corrupt the capture at that same edge. Every timing exception is ultimately a statement about which edges the tool should pair.

9. What is a virtual clock and when do you use one?
A clock created with create_clock -name and no source object — it exists in the SDC but drives nothing in the netlist. It is the reference for set_input_delay and set_output_delay when block I/O is timed against a system clock that never enters the block, modeling the external launch or capture flop. Standard practice in block-level SDC handoff.

10. How does latch-based time borrowing work?
A level-sensitive latch is transparent for an entire clock phase, so data may arrive after the opening edge and borrow into the transparency window — up to the closing edge minus setup — pushing the deficit to the next stage instead of failing immediately. Intel asks this constantly because their designs are historically latch-rich.

Intermediate: questions 11-20

This tier decides whether the panel writes you up as a tool operator or a timing engineer.

11. Explain OCV, AOCV, and POCV.
All three model on-chip variation. Plain OCV applies a flat derate to every path — simple and brutally pessimistic. AOCV derates by path depth and distance, since random variation averages out over more stages. POCV models each cell's delay statistically (mean plus sigma) using LVF (Liberty Variation Format) library data, giving the tightest silicon-accurate numbers. POCV with LVF is the signoff standard at 7nm and below.

12. What is CRPR and why does it matter?
Clock reconvergence pessimism removal (CPPR in Cadence tools). Launch and capture clocks usually share part of the clock tree, but OCV derates that shared segment slow on one side and fast on the other — physically impossible, since one wire has one delay per cycle. CRPR computes the pessimism on the common segment and credits it back, as its own line in report_timing. Without it, teams burn area and power fixing violations that do not exist.

13. When do you declare a false path, and when should you refuse to?
Declare it on paths never exercised functionally: properly synchronized CDC crossings, static configuration registers programmed before functional mode, mutually exclusive mode muxing. Refuse when a CDC path lacks a proper synchronizer — the false path would hide a real bug — or when the true intent is multicycle. In a signoff review you defend every false path in the deck; "the tool couldn't close it" is how constraint decks kill chips.

14. How does a multicycle path work, and what is the classic mistake?
set_multicycle_path -setup N moves the setup capture edge N cycles after launch. But the hold check then defaults to N−1 cycles after launch, which is almost never the intent — add -hold N-1 to pull the hold check back to the launch edge. Forgetting the hold adjustment produces a wall of false hold violations. Interviewers always ask for the edge diagram — draw it.

15. When do you use set_max_delay and set_min_delay instead of clock-based checks?
They are point-to-point overrides that replace the derived clock relationship with an absolute delay bound. Use them for asynchronous clock crossings that still need bounded latency — gray-coded FIFO pointers are the canonical case — for purely combinational paths, and for latency-critical routes with a hard budget.

16. What is the precedence order among timing exceptions?
set_false_path wins over set_max_delay/set_min_delay, which win over set_multicycle_path. Within the same command type, the more specific object list wins: a -from pin beats a -from clock. Interviewers hand you two overlapping exceptions and ask which applies.

17. What are recovery and removal checks?
Setup and hold analogues for asynchronous control signals against the clock — typically reset deassertion. Recovery requires the async signal stable a window before the active edge; removal, a window after. Violate them and flops sample reset release metastably — a class of bugs that appears only in silicon. STA still checks recovery/removal on the synchronized deassert paths.

18. How does timing change for a posedge-to-negedge path?
It becomes a half-cycle path: with a 50% duty cycle the setup check gets only half a period, while the hold check moves to the previous opposite edge and is usually easy to meet. Duty-cycle distortion now enters the math directly, because the high and low pulse widths set the real budget. Common in DDR interfaces and around clock-gating cells.

19. Where do max_transition and max_capacitance violations fit in signoff?
They are design-rule violations (DRVs) and must be clean before any slack number is trusted. Library delay models are characterized over a bounded slew and load range — a cell outside that range has an extrapolated, invalid delay, so the DRV undermines the timing data itself. Fix by upsizing drivers, buffering long nets, splitting high fanout — and check DRVs before anyone looks at WNS.

20. Ideal versus propagated clocks — when is each used?
Pre-CTS, clocks are ideal: zero network delay, with set_clock_uncertainty carrying the budget for the tree you have not built yet. Post-CTS, you switch to propagated clocks so real insertion delays and skew enter every check, and cut uncertainty down to jitter plus margin. Running the wrong mode gives garbage in either direction — propagated pre-CTS shows fake violations, ideal post-CTS hides real ones.

Advanced: questions 21-26

Staff-level differentiators — and the core of Synopsys and Cadence AE interviews.

21. What is useful skew, and what does it cost?
Deliberately unbalancing the clock tree so a setup-critical endpoint's capture clock arrives late, borrowing time from the following stage. The costs: hold exposure at the same endpoints, extra clock buffers (power, insertion delay), and ECO fragility — a tree tuned to one netlist revision fights the next. Apply it endpoint-by-endpoint through CTS ECO, then re-verify hold at every fast corner. NVIDIA rounds go deepest here; blocks above 2 GHz live on useful skew.

22. 500 setup violations post-route, RTL frozen. Walk through your ECO plan.
Triage by TNS per path group, not just WNS. Paths failing by under ~30 ps: re-run in PBA — many recover for free. Small real failures: footprint-compatible VT swaps (LVT/SLVT, paying leakage) and cell sizing. Structural failures: buffer restructuring, promoting long nets to upper metal, useful-skew CTS ECO. In parallel, re-run with SI disabled to isolate crosstalk-dominated paths — those need spacing or shielding, not sizing. If your answer starts with "upsize everything," you have never met the hold-and-leakage ping-pong at the end of that road.

23. What is MCMM, and what does a 2026 signoff corner list look like?
Multi-corner multi-mode: analysis scenarios are the cross product of modes (mission, scan shift, scan capture, low-power states) and corners (process, voltage, temperature, RC extremes). Advanced-node signoff commonly runs 20-50+ scenarios on distributed PrimeTime or Tempus. The trap: at low-voltage FinFET nodes, temperature inversion means worst setup is often at SS low temperature, not high. Saying "setup at SS 125C, always" dates your knowledge to 28nm — Qualcomm panels use exactly this probe.

24. How are timing derates actually chosen?
From foundry variation guidance, internal margin methodology, and silicon correlation history — not folklore. Flat derates via set_timing_derate are applied separately for early/late, clock/data, launch/capture; AOCV and POCV replace flat guesses with depth-based tables or sigma values from LVF libraries. The honest answer acknowledges that derates are a negotiated margin stack owned by a signoff methodology team. Reciting "1.05 and 0.95" with no reasoning fails the question.

25. Graph-based versus path-based analysis?
GBA propagates the worst slew at each pin regardless of which path produced it — fast, but pessimistic. PBA re-times a specific path using its actual slews and per-path derates — accurate, but expensive. Production signoff runs GBA everywhere, then PBA on violating endpoints to recover pessimism before spending ECO effort. At Synopsys and Cadence AE interviews this becomes an algorithms discussion: why GBA is safe, and what path versus exhaustive recalculation modes trade off.

26. How is AI changing STA in 2026?
Three real deployments: ML-guided ECO in the signoff tools (PrimeTime's ML-driven fixing, Cadence Cerebrus feeding Tempus ECO loops) that predicts which fixes converge without disturbing routing; models trained on earlier blocks that predict post-route slack from pre-route features, cutting full-flow iterations; and RL-based flow tuning (DSO.ai, Cerebrus) selecting effort and margin recipes. Be honest about your exposure, precise about the concepts — and never claim signoff is "solved by AI."

Tool-specific: questions 27-30 (PrimeTime and Tempus)

PrimeTime dominates Synopsys-flow shops (Intel, Samsung); Tempus rules Cadence-flow houses (NVIDIA, much of Qualcomm). Learn one deeply — command fluency is treated as a proxy for hands-on hours. For the full tool landscape, see the EDA tools for physical design guide.

27. Which report_timing options do you use daily?
-from/-through/-to for path selection; -delay_type min for hold (max is the default setup view); -path_type full_clock_expanded to see the entire clock network; -nworst and -max_paths for breadth; -input_pins -transition_time -capacitance for the debug columns; crosstalk delta annotation for SI-suspect paths. Engineers who have closed timing rattle these off cold.

28. Walk me through reading a PrimeTime timing report.
Header first: startpoint, endpoint, scenario, path group. Then the clock sections before the data section — check whether clocks are ideal or propagated, and compare launch versus capture network delay, because skew problems hide there. In the data section, scan the incr column for big jumps (weak cell or long net) and asterisks marking annotated SI delta delays. Then uncertainty, the CRPR credit line, and slack. Most "logic delay" problems turn out to be clock problems.

29. What do you run before trusting any timing number?
check_timing — unconstrained endpoints, unclocked registers, missing input/output delays, combinational loops, multiple clocks reaching one register. Then report_analysis_coverage for the percentage of endpoints actually checked, and report_constraint -all_violators for DRVs. A beautiful WNS on a design that is 60% constrained is fiction.

30. Describe the STA-driven ECO loop end to end.
In PrimeTime: fix_eco_timing for setup/hold and fix_eco_drc for transitions and cap, in physical-aware mode with LEF/DEF loaded; write_changes exports the edits in ICC2 or Innovus format; the PnR tool applies them, incrementally places and routes, then you re-extract and re-run STA across scenarios. Tempus drives the same loop through its signoff optimization flow. Expect 2-5 iterations, with hold fixed after setup stabilizes.

Which companies emphasize what

• Qualcomm (Bangalore, Hyderabad). MCMM at scale: low-power modes, voltage scaling, scenario explosion at 4nm/3nm, UPF-aware timing. Expect the temperature-inversion probe.
• Intel (Bangalore). Methodology rigor: derate justification, latch borrowing, constraint quality, check_timing discipline. They care how you know a number is trustworthy.
• NVIDIA (Bangalore, Pune). High frequency: useful skew, PBA at scale, Tcl automation of timing debug. Expect live scripting questions.
• Synopsys and Cadence AE roles (Noida, Bangalore, Hyderabad). Teach-the-tool depth: GBA/PBA mechanics, why PrimeTime and Tempus disagree on the same path, correlation debug.
• Service companies (LTTS, Wipro VLSI, HCL, Tata Elxsi). Flow familiarity and report reading across client tools; lower depth bar, wider breadth.

How to prepare, and what it pays

The prep that works: derive setup and hold from first principles with edge diagrams until automatic; do twenty hand-calculation slack drills with skew, latency and uncertainty in the numbers; pull real timing reports from a block you shipped and re-explain your ten worst paths out loud; learn one tool's command set cold. Three to four weeks is enough for a mid-level engineer. If you are unsure which area is weak, run the free skill-gap analysis on semiconductor.cv — it compares your resume against live PD and STA job requirements and tells you what to close first.

On compensation: STA depth is the biggest lever inside the PD ladder. Engineers with 3-6 years who can own timing closure and signoff land 25-45 LPA at product companies versus 12-18 LPA at service companies; dedicated signoff leads clear 50 LPA. Full bands by specialization and experience are in our salary guide. Then match your prep to the market: browse current physical design and timing openings and prep to the JDs, not a syllabus.

Related reading

• Physical Design Interview Questions: The Complete Guide for India (2026)
• Top EDA tools every physical design engineer must know in 2026
• VLSI salary guide: bands by specialization and experience