DFT Engineer Career & Interview Guide: The Specialisation No One Explains in College (India 2026)

TL;DR. DFT (Design for Test) is the specialisation no one explains in college. It is the chip-design discipline that ensures every transistor on every die can be tested at scale, which is the difference between a fab shipping working silicon and a fab shipping bricks. In India in 2026, DFT engineers are among the most consistently hired and least well understood VLSI roles. This guide explains what DFT engineers actually do, the career path from fresher to staff, the salary numbers, the interview format, and the 30 questions I see most often when hiring.

I have spent 10 years in DFT — eight at Broadcom and Texas Instruments, two leading a team — and I have seen the same pattern with most candidates I have interviewed. They know what scan is. They cannot explain why scan compression exists, what the trade-off is, or how MBIST and ATPG fit together at silicon bring-up. Closing that gap is what gets DFT engineers hired into product companies.

What does a DFT engineer actually do?

A DFT engineer makes a chip testable. Concretely, that breaks down into five activities, every one of which is a multi-month project on a real SoC.

1. Scan insertion. Stitching every flop in the design into shift registers (scan chains) so the chip can be set to any state and any state can be observed.
2. ATPG (Automatic Test Pattern Generation). Running tools (Synopsys TestMAX, Cadence Modus, Mentor Tessent) to generate the patterns that detect manufacturing defects via the scan chains.
3. MBIST (Memory BIST). Inserting on-chip memory test logic so RAMs and ROMs can self-test in the field, since you cannot scan-test a memory array efficiently.
4. Boundary scan and JTAG. Implementing IEEE 1149.1 to enable board-level test, debug, and programming.
5. Silicon bring-up and yield analysis. When the chip comes back from the fab, DFT runs the tester programs, identifies defective dies, and works with the fab to improve yield. This is where DFT careers compound — silicon experience separates senior DFT engineers from juniors.

What DFT does not do: write functional RTL, run gate-level simulations of system behaviour, or close timing on the data path. DFT works adjacent to the design team, not as the design team.

Why DFT pays well in India

Experience	Salary range (LPA)	Top companies
Fresher (0-2 years)	6-14	Texas Instruments, Broadcom, Qualcomm, Intel
Mid (3-5 years)	14-28	NVIDIA, AMD, Marvell, Synopsys
Senior (6-10 years)	28-50	Qualcomm, Apple India, Google, Microsoft
Staff and Principal (10+ years)	50-90	NVIDIA, Apple, Google, Qualcomm

DFT salaries sit slightly below RTL design at the fresher level and roughly equal to physical design at senior level. The reason: DFT is in shorter supply than RTL or PD because the discipline is rarely taught well at the undergrad level. Companies retain DFT engineers aggressively — silicon experience does not transfer easily, and a DFT lead with three successful tape-outs is hard to replace.

The DFT skill stack

If you are considering a DFT career, this is the skill stack hiring managers look for, ordered from foundational to advanced.

1. Verilog and SystemVerilog — read fluently, write basic testbenches.
2. Scan architectures — full scan, partial scan, mux-D, LSSD; trade-offs in coverage, area, and timing.
3. EDA tools — at least one of Synopsys TestMAX (DFT Compiler, TestMAX ATPG), Cadence Modus, or Mentor Tessent.
4. Tcl scripting — every DFT flow runs on Tcl. Production scripts are 1000s of lines.
5. Static timing analysis (STA) — DFT structures must close timing in scan mode and functional mode separately.
6. Power and clock gating — DFT changes clock topology; you must understand the implications.
7. MBIST insertion — wrappers, repair logic, test modes.
8. JTAG and boundary scan — TAP controller, BSDL files, board-level integration.
9. Tester programs and silicon bring-up — STIL, WGL, test program structure on Advantest or Teradyne testers.
10. Yield analysis — diagnostic ATPG, defect localisation, statistical yield modelling.

The first six are sufficient to land a DFT role at a service company or a fresher slot at a product company. Items 7-10 are what separates a 3-year DFT engineer from a 7-year one.

The DFT interview format in 2026

Five rounds at most product companies, similar to RTL, with the technical content shifted toward DFT-specific topics.

1. Recruiter screen. CTC, notice period, location preference.
2. Technical screen (45-60 min). Foundational DFT questions, sometimes with a small live exercise on scan stitching or ATPG flow.
3. Onsite DFT deep dive (60-75 min). Walk through a DFT flow end-to-end. Trade-offs in scan compression, MBIST coverage, AT-speed test.
4. Onsite STA and integration (45-60 min). How DFT structures interact with timing, clock gating, low-power features.
5. Hiring manager (30-45 min). Past project, silicon experience, debugging stories.

30 DFT interview questions with answers

Foundations (Q1-Q8)

Q1. What is scan and why do we need it?

Scan converts every flip-flop in a design into a 2-input mux followed by a flop. In test mode, the muxes form a long shift register that lets us load any state into the design and read any state out. Without scan, observing the internal state of a chip with a billion flops at a tester is impossible. With scan, every flop is fully controllable and observable in O(N) shift cycles, where N is the chain length.

Q2. What is the difference between full scan and partial scan?

Full scan stitches every flop into the scan network. Partial scan stitches only some flops. Full scan is the default in 2026 because ATPG coverage on partial-scan designs is much lower and the area overhead of full scan is acceptable on modern process nodes. Partial scan still appears in legacy automotive ICs and ultra-low-power designs.

Q3. Explain stuck-at-0 and stuck-at-1 fault models.

The simplest defect models. A stuck-at-0 fault assumes a node is permanently shorted to ground, regardless of what the logic drives. Stuck-at-1 assumes it is shorted to VDD. ATPG generates patterns that exercise every node such that a fault would propagate to an observable output. Stuck-at coverage above 99 percent is the bar for production silicon.

Q4. What is at-speed test and why is it important?

Standard scan tests run at low frequency. At-speed test launches a transition from one flop to the next at functional clock speed and captures the result, catching delay defects that stuck-at testing misses. Two main schemes: launch-on-shift (LOS) and launch-on-capture (LOC). LOC is more conservative (no constraint on shift-clock skew), LOS gets higher coverage but requires fast scan-enable signals.

Q5. What is scan compression and what is the trade-off?

Scan compression reduces the test data volume by adding decompressors and compactors around the scan chains. Effective compression ratios of 50-100x are routine on modern designs. Trade-off: more area, more clocking complexity, and reduced observability of certain fault types. Every product company uses compression; service companies sometimes skip it for low-cost designs.

Q6. Explain the difference between MBIST and ATPG.

ATPG generates patterns that detect manufacturing defects in random logic (combinational and sequential gates) via the scan chains. MBIST is a self-test built into each memory block — a small state machine that walks address sequences (March, Walking 1s, Checkerboard) and checks the read data. You cannot scan-test memory efficiently because there are too many cells; MBIST gives O(N) test time on N memory cells.

Q7. What is JTAG and how does it relate to DFT?

JTAG (IEEE 1149.1) is a 4-wire serial interface (TCK, TMS, TDI, TDO) standard for board-level test access. It exposes a TAP (Test Access Port) controller on every chip. JTAG enables boundary scan, on-chip debug, MBIST control, scan chain access, and increasingly, secure debug protocols. Every modern SoC has a JTAG TAP.

Q8. What is boundary scan?

Boundary scan adds a scan cell at every chip pin so the connections between chips on a PCB can be tested without physical probes. Implements the full IEEE 1149.1 standard. The output is a BSDL (Boundary Scan Description Language) file that PCB test tools consume.

Scan and ATPG (Q9-Q15)

Q9. How do you decide the number of scan chains for a design?

Two constraints set the number. (1) Tester pin count: each scan chain needs a scan-in and scan-out pin (or pin-shared with functional pins). Testers limit how many chains you can drive simultaneously. (2) Test time: total test time is roughly chain-length divided by chains-in-parallel. Real designs use compression, which decouples chain count from pin count — modern designs run 200-2000 internal chains feeding a much smaller compressed external interface.

Q10. What is shadow logic and how do you handle it in ATPG?

Shadow logic is combinational gates whose output goes only to non-scan elements (e.g., black-box memories, analog blocks). ATPG cannot observe these outputs, so coverage drops. Solutions: scan-wrap the boundary of the black box, add observation flops, or accept the coverage loss and document it in the test plan.

Q11. What is launch-on-capture (LOC) timing?

In LOC, the scan-enable signal is held inactive across two functional clock pulses. The first pulse launches a transition from a flop. The second pulse captures the result. The path under test runs at functional speed. Critical timing constraint: scan-enable must be stable at functional clock speed during the at-speed window, which means it must be either pipelined or low-skew.

Q12. What is launch-on-shift (LOS)?

In LOS, the scan-enable transitions from active to inactive between the launch and capture clock edges. The transition is launched by shifting in a new value, then captured at functional speed. Higher fault coverage than LOC for many fault models, but requires scan-enable to switch at functional frequency — harder to implement on large designs.

Q13. What is X-bounding and why does it matter?

X-bounding is the practice of forcing unknown values (X) at sources of indeterminism (asynchronous interfaces, uninitialised memories) into a known state during ATPG. Unbounded Xs propagate, corrupting captured signatures and tanking coverage. Modern tools handle most X-bounding automatically but DFT engineers still review and add manual constraints around custom blocks.

Q14. What is fault grading?

Fault grading measures the percentage of modelled faults a given test pattern set detects. Stuck-at coverage, transition fault coverage, and bridging fault coverage are tracked separately. Tape-out gates typically require 99-99.5 percent stuck-at and 90-95 percent transition coverage.

Q15. Explain test compression decompressor architectures.

Two main families. (1) Linear (XOR-network) decompressors that expand a small set of input pins to many internal scan chain inputs. (2) Reseeding-based architectures (Synopsys DFTMAX, Mentor EDT) that broadcast seed values to LFSRs feeding the chains. Compactors at the output side compress the responses. Each vendor implements variants; the principles transfer.

Memory test and JTAG (Q16-Q22)

Q16. Walk through MBIST insertion for a 1MB SRAM.

Steps: select a March algorithm appropriate for the memory's defect profile (March-C for SRAM is common). Generate a wrapper that includes the BIST controller, the comparator, the address generator, and the data generator. Connect to the JTAG TAP for control. If repair is needed (large memories), include a fuse-programmable column or row repair register. Run timing closure on the wrapper at functional speed.

Q17. What is memory repair?

Large memories have non-zero defect rates. Memory repair adds redundant rows or columns and fuse-programmable steering logic. At test time, defective rows are mapped to redundant ones via fuses programmed by the tester. Repair pushes effective yield from unusable to acceptable on memory-heavy designs.

Q18. Explain the JTAG TAP state machine.

16 states, transitions controlled by TMS sampled on rising TCK. Two main paths: Data Register (DR) and Instruction Register (IR). The TAP starts in Test-Logic-Reset, and TMS sequences move it through Run-Test-Idle, Select-DR-Scan, Capture-DR, Shift-DR, etc. Every JTAG operation is a sequence of these state transitions.

Q19. What is BSDL and who consumes it?

BSDL (Boundary Scan Description Language) is a VHDL-subset format that describes a chip's JTAG implementation: pin list, instruction codes, boundary scan cell ordering. PCB-level test tools (Goepel, ASSET, JTAG Technologies) consume BSDL files to generate board-level interconnect tests.

Q20. What is IJTAG?

IEEE 1687, an extension to JTAG for embedded instrument access. Where 1149.1 was designed for boundary scan, 1687 was designed for the modern reality where chips have hundreds of embedded test, debug, and configuration instruments. IJTAG networks let test engineers access these instruments through the same TAP without manually managing each one.

Q21. What is the difference between hard fuses and soft fuses?

Hard fuses (e-fuse, anti-fuse) are one-time-programmable in silicon. Used for memory repair, security keys, and trim values. Soft fuses are software-programmable registers that mimic fuse behaviour during test, used for debug and post-silicon validation before committing to hard fuses.

Q22. How do you handle on-chip clock generation in DFT?

On-chip PLLs, DLLs, and ring oscillators must be bypassed in scan mode so the tester can drive a clean external clock. Add scan-mode bypass muxes around clock generation blocks. For at-speed tests using the on-chip PLL, add a separate at-speed clock controller that gates between scan-shift and at-speed-capture frequencies.

Silicon bring-up and yield (Q23-Q30)

Q23. The chip comes back from the fab. Walk me through bring-up.

Step 1: power-on the device on a bench, verify rails. Step 2: load a tester program with the simplest pattern (continuity, leakage). Step 3: run JTAG IDCODE — first sign the chip is alive. Step 4: run scan structural patterns. Step 5: run MBIST. Step 6: run at-speed scan. Step 7: hand to the system team for functional bring-up. DFT lives in steps 1-6.

Q24. The yield is 40 percent. What do you do?

Run diagnostic ATPG on a sample of failing units. The diagnostic tool maps test failures back to physical defect locations. Aggregate the failures across hundreds of dies and look for patterns: hot spots on a particular layer, systematic via failures, edge-of-die clustering. Hand the results to the fab. Yield improvements happen iteratively across silicon revisions.

Q25. What is a hard repair vs soft repair?

Hard repair burns fuses to remap defective memory addresses permanently. Soft repair stores the repair map in volatile registers loaded on every power-on. Hard repair commits silicon, soft repair allows re-evaluation across test conditions. Most production flows use hard repair after qualification.

Q26. Explain shift power.

During scan shift, every flop in the scan chain may toggle on every shift clock — millions of transitions per cycle. This consumes huge dynamic power, drops core voltage (IR drop), and stresses the package. Mitigation: low-power scan techniques such as MUX-toggle suppression, shift gating, and clock domain isolation during shift.

Q27. What is IDDQ testing and is it still used?

IDDQ measures the static current draw with the chip in a known idle state. A higher-than-expected static current indicates a stuck-at-X defect or short. IDDQ was once a primary test methodology but has lost favour at advanced nodes because leakage current overwhelms defect signal. Still used selectively at older nodes (40nm and above) and in high-reliability automotive parts.

Q28. What is logic BIST (LBIST)?

Self-test for logic that runs on-chip without a tester, using a pseudo-random pattern generator (LFSR) to drive scan chains and a signature analyser to compress responses. Used in safety-critical applications (automotive ASIL-D, aerospace) where the chip must self-test in the field. Lower coverage than ATPG but no tester needed.

Q29. What is scan compression's effect on diagnostic resolution?

Compression reduces test time and pin count but hurts diagnostic resolution because the compactor mixes responses from many chains. To compensate, modern flows include a diagnosis-mode that bypasses or partially bypasses the compactor. Diagnosis takes longer but localises faults precisely.

Q30. Walk me through a real silicon problem you debugged.

Hiring managers want a story. Pick something specific. Example: "On A0 silicon of an automotive SoC, MBIST passed at room temperature but failed across a small number of dies at -40C. We ran diagnostic MBIST, isolated the failures to one specific column in the L2 cache. Cross-referenced with the failing dies' wafer position — they clustered at one wafer edge. The fab traced it to a marginal lithography step at that edge. We added a more aggressive March pattern to catch the marginal cells, and the column repair logic mapped them out for the affected wafers." Specific is the entire point.

Career path: fresher to staff DFT engineer

Years	Title	Responsibilities
0-2	DFT Engineer	Run scan insertion and ATPG flows, write basic Tcl, support tape-out checklists. Reads tool manuals constantly.
2-5	DFT Engineer / Senior DFT	Own scan and ATPG for one or two blocks, contribute to silicon bring-up, debug failing patterns, develop reusable Tcl flows.
5-10	Senior / Lead DFT	Own end-to-end DFT for a chip, define methodology, lead silicon bring-up, mentor juniors, drive yield analysis cycles with the fab.
10+	Staff / Principal DFT	Methodology architect across multiple chips, evaluate new EDA tools, set DFT roadmap for the org, drive silicon-validation correlation.

How to get into DFT as a fresher

DFT is rarely taught as a course in Indian colleges. The path that works:

1. Solid digital design and Verilog fundamentals from your undergrad coursework.
2. One semester project that involves a DFT step — adding a JTAG TAP, running a scan stitch, generating ATPG patterns. EDA vendors (Synopsys, Cadence, Siemens) offer university programmes that include DFT tools.
3. An internship at a service company (Wipro, LTTS, HCL) on a DFT project. Service companies hire freshers more aggressively than product companies and the work is real.
4. Two to three years of solid service-company DFT, then transition to a product company. Product companies hire DFT engineers with proven scan and ATPG experience even without IIT credentials.

Where to go from here

If DFT sounds interesting and you are weighing it against other paths, read our comparison of RTL, verification, and physical design for the broader context. For salary expectations across all VLSI specialisations, see the India 2026 salary guide. If you are coming from IT services and weighing a switch, the 3-5 year career switch guide covers the realistic transition path.

Browse live DFT engineer roles aggregated directly from chip-company career pages — Texas Instruments, Broadcom, Qualcomm, Intel, NVIDIA, AMD, and 25+ others.