Stage Ingénieur : Conception Numérique SoC - Design for Test (F/H)

What You'll Do

• will include: Understanding the DFT architecture implemented within our SoCs.
• Learning and using the Computer-Aided Design (CAD) environment dedicated to DFT activities.
• Developing test sequences to achieve optimal fault coverage.
• Performing simulation, analysis, and debugging of test sequences.
• Evaluating DFT methodologies and identifying opportunities for flow improvements.
• Collaborating with design, verification, and implementation teams throughout the development cycle.
• Documenting findings and presenting progress and results to the project team.
• Profile Education Currently pursuing a Master's degree in Electrical Engineering, Microelectronics, Computer Engineering, or a related field.
• Strong interest in digital integrated circuit design, verification, and test methodologies.
• Technical Skills Experience with RTL design and simulation using VHDL and/or Verilog.
• Good understanding of digital logic design and semiconductor fundamentals.
• Knowledge of Design-for-Test (DFT) concepts; exposure to production testing is considered a plus.
• Familiarity with scripting and programming languages such as: Python, Perl, Tcl Personal Skills Self-motivated, proactive, and eager to learn.
• Strong analytical and problem-solving capabilities.
• Good communication and teamwork skills.
• Comfortable working in an international environment .
• Languages Good level of French and English communication skills, both verbal and written More information about NXP in France... #LI-3842