Senior Principal Verification Engineer, Digital IP

Qualifications

• Degree in Electrical Engineering or Computer Science, with 7+ years of experience on IP/Sub-System Verification Prior experience as a tech lead or DV manager is strongly preferred Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
• Advanced knowledge of Verilog, SystemVerilog, C/C++, Shell.
• High proficiency in Metric Driven Verification concepts, functional and code coverage.
• High proficiency in directed and constrained random methodologies.
• Good knowledge of formal verification methodologies and assertions.
• Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
• Excellent written and verbal communication skill.
• Good knowledge in scripting like Perl, TCL or Python is a plus More information about NXP in India... #LI-29f4