Senior Principal SoC Physical Implementation/STA Engineer

What You'll Do

• RTL synthesis including equivalence and low-power checks, design ECO.
• Static Timing Analysis (STA), includes working with the architecture and front-end designers to develop and verify timing constraints, perform hierarchical timing budgeting and analysis, create ECOs and drive timing closure for sub-system and SOC.
• Physical Design of key critical subsystem implementation.
• Contributes to problem solving related to STA and physical design.
• Your profile To be successful in this role you must have: BS or MS in Electrical or Computer Engineering.
• Expertise in STA, including timing constraints development and timing closure.
• Knowledge of Synthesis, LEC , low power checks. ..
• Knowledge of Physical Implementation ( Place&Route ) is a plus.
• Knowledge of deep sub-micron CMOS process technology.
• Strong analyzing skills and problem-solving attitude.
• Effective communication skills to operate in a global environment.
• Strong automation skills with Perl, Phyton, TCL...
• More information about NXP in France... #LI-7795