Senior HW Digital Design Verification Engineer

What You'll Do

• Develop and execute detailed verification plans for complex digital blocks and sub-systems, including testbench architecture, testcase development, and coverage closure. - Implement advanced verification methodologies such as UVM (Universal Verification Methodology) and formal verification techniques. - Create and maintain verification environments using industry-standard tools and languages (e.g., SystemVerilog, UVM, OVM, e). - Develop directed, constrained-random, and assertion-based testbenches to thoroughly validate design functionality and performance. - Perform functional and code coverage analysis to ensure verification completeness. - Debug complex design and verification issues, working closely with design engineers to identify root causes and propose solutions. - Collaborate with design, architecture, and software teams to understand design specifications and requirements. - Contribute to continuous improvement of verification methodologies, flows, and tools. - Mentor junior engineers and share technical expertise within the team.
• Job Qualifications - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. - 5+ years of experience in digital design verification of complex ASICs/SoCs. - Strong proficiency in SystemVerilog and UVM. - Demonstrated experience in developing comprehensive test plans and verification environments from scratch. - Solid understanding of digital design principles, computer architecture, and communication protocols. - Experience with industry-standard EDA verification tools (e.g., simulators, waveform viewers, coverage analysis tools). - Familiarity with scripting languages (e.g., Python, Perl, Tcl). - Experience with formal verification techniques is a plus. - Excellent problem-solving, analytical, and debugging skills. - Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment.
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