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What You'll Do
- Implement and execute verification for IP blocks and sub‑systems using SystemVerilog and UVM, following established verification methodologies and plans.
- Develop and enhance UVM components, including agents, monitors, drivers, scoreboards, assertions, and functional coverage models.
- Author and execute test plans and testcases, including directed and constrained‑random tests, to validate functional correctness and corner cases.
- Contribute to verification closure, analyzing coverage results, identifying gaps, and adding tests or coverage points to meet sign‑off requirements .
- Participate in low‑power verification, assisting with UPF/CPF integration and validating power‑related scenarios under guidance.
- Assist in HW–FW co‑verification, including development and execution of C/C++ tests for simulation or prototyping platforms.
- Debug RTL issues, collaborating with design engineers to resolve functional mismatches, assertion failures, and coverage holes.
- Execute and maintain regressions, triaging failures and ensuring stability of the verification environment.
- Review specifications and design documents, raising questions and identifying potential verification risks early in the development cycle.
- Work closely with peers and senior engineers, contribute to team deliverables and continuously improving verification quality.
- Qualifications / Skills Hands‑on experience in ASIC/IP verification, with at least one or more tape‑out cycles in a professional semiconductor environment.
- Good proficiency in SystemVerilog and UVM, with experience developing test benches and testcases.
- Working knowledge of core verification concepts, including: Test planning and execution Directed and constrained‑random stimulus Functional and code coverage Basic assertion‑based verification Introduction to low‑power verification concepts Exposure to C/C++ programming for verification or HW–FW interaction.
- Basic scripting skills (Python, Perl, or similar) for automation and debug support.
- Experience using version control and issue‑tracking tools, such as Git and Jira.
- Strong problem‑solving skills, attention to detail, and willingness to learn, with the ability to take ownership of assigned verification tasks.
- Effective written and verbal communication skills , and ability to work well within a team environment.
- More information about NXP in India... #LI-29f4
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at NXP Semiconductors
129 positions
Job ID
/job/Pune/Senior-Digital-Verification-Engineer_R-10061637
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