Senior Analog Layout Engineer

Overview

• High Performance Analog (HPA) PL is looking for a Senior Layout Design Engineer who will be responsible for chip and block level layout of high-performance analog and mixed-signal products.
• A successful candidate will operate as the lead layout design engineer for the PL.
• The candidate will set up and debug LVS, DRC, ERC environments for the project team, as well as collaborate with lead chip design engineer on chip-level floor-plan.
• In addition, the candidate will layout critical building blocks such as high-resolution (e.g.
• 24-bit) analog-to-digital converters, precision voltage references, and HV chopper-stabilized amplifiers.
• As the lead layout design engineer of the PL, the candidate will also mentor fellow layout design engineers on techniques and best practices for high-precision and low-noise analog designs.
• As a key member of the team, you will be responsible for: · Driving/delivering floorplan activities at both IPs and/or SOC level.
• · Participating to the power supply strategy, signals distribution between blocks.
• · Delivering Analog layout blocks and/or top floorplan strategy.
• · Driving the top-level integration using the Mixed Signal on Top flow.
• · Leading a layout team for the SoC execution and scheduling its activities through the project.
• · Running all physical verifications as DRC/LVS/DFM and parasitic extractions to achieve high quality layout deliveries.
• · Participating to design reviews, write documentation and support for integration into products.
• · Having a strong focus on design for quality (designs are properly verified, validated, and tested for long-term reliability and zero defect).
• · Identifying root cause and solutions for issues identified on 1st prototypes.
• · Being able to leverage layout expertise to provide technical training and write technical guidelines.
• The ideal candidate will have: · >10+ years of experience leading Analog layout activities in complex ICs.
• · Strong expertise in Analog layouts, device physics and IC ESD protection strategies.
• · Expert in layout design tools such as Cadence Virtuoso (OA, PVS) and Mentor Graphics (Calibre).
• · Ability to drive and collaborate with experienced people having different technical profiles.
• · Ability to manage and drive a multisite layout team.
• · Experience in delivering advanced floorplan strategies.
• · Experience in physical implementation in Analog blocks at IPs and/or SOC level.
• · Ability to leverage his expertise to provide training, support and write guidelines focused on layout activities.
• · Experience with cross functional teams and excellent communication skills to operate in a global environment with multiple partners in design, test, program management, quality department.
• More information about NXP in Italy..