Physical Design Methodology Lead

What You'll Do

• Own, develop, and continuously improve backend RTL-to-GDS implementation flows for advanced process nodes, with emphasis on quality of results, scalability, runtime, and designer productivity.
• Drive methodology development across place and route, CTS, timing closure, congestion analysis, ECO implementation, power grid design, IR/EM analysis, extraction, and signoff readiness.
• Partner with design, architecture, DFT, verification, timing, low-power, package, foundry, and signoff teams to ensure flows meet tapeout requirements for complex SoC and IP programs.
• Lead initiatives from concept and feasibility assessment through prototype development, benchmarking, validation, documentation, deployment, training, and production support.
• Establish repeatable best practices, reference flows, automation frameworks, dashboards, and metrics to improve PPA, reduce turnaround time, and improve predictability across projects.
• Work closely with EDA vendors to evaluate, enable, and adopt the latest technologies in physical implementation, signoff, power integrity, machine learning optimization, and agentic/AI-assisted design automation.
• Conduct competitive benchmarking and technology evaluations to identify flow gaps, quantify benefits, and influence vendor roadmaps.
• Debug complex flow, tool, constraint, timing, power, congestion, and physical verification issues, and provide expert guidance to design implementation teams.
• Promote automation-first thinking through scripting, reusable infrastructure, regression systems, data-driven flow analysis, and intelligent decision support.
• Provide deployment support, training, and hands-on technical leadership to ensure new methodologies are adopted effectively across engineering teams.
• Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• Typically 15+ years of experience in physical design, backend implementation, CAD, design automation, or flow and methodology development for ASIC or SoC products.
• Strong hands-on expertise with RTL-to-GDS implementation flows, including synthesis, floorplanning, placement, CTS, routing, optimization, extraction, timing closure, ECO, and physical verification.
• Deep understanding of timing signoff, constraints, STA debug, SDC methodology, multi-corner multi-mode closure, setup/hold optimization, and correlation across implementation and signoff tools.
• Experience with power grid design, IR drop, EM analysis, low-power implementation, multi-voltage design, UPF-based flows, and power optimization techniques.
• Proven ability to improve PPA through methodology innovation, tool tuning, automation, and cross-functional problem solving.
• Strong scripting and automation skills using Tcl, Python, Perl, shell scripting, or equivalent technologies.
• Experience working with leading EDA platforms from vendors such as Synopsys, Cadence, Siemens EDA, or equivalent tool ecosystems.
• Demonstrated ability to influence technical direction, communicate complex topics clearly, and drive cross-team initiatives to closure.
• More information about NXP in India... #LI-2734