Physical Design Lead

Nice to Have

• Experience leading physical implementation and signoff for large-scale SoCs across multiple engineering sites.
• Experience developing organization-wide design methodologies, automation frameworks, and best practices.
• Strong understanding of advanced-node challenges including congestion management, variation-aware timing closure, power integrity, and reliability signoff.
• Experience evaluating and deploying next-generation EDA technologies and AI-assisted design optimization techniques.
• More information about NXP in India... #LI-9415