Physical Design engineer

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What You'll Do

  • As part of a large international R&D organization, you need to work closely with SoC cross functional teams to develop and define Physical Design methodology to meet SoC & IP level objectives on low geometry nodes (5/14/16/28/40nm). • Your scope of work will cover tools and flow definition, requirement management for SoC and IP level Synthesis, UPF, formal verification, floor plan, power plan, IO ring, Place & Route, DRC, ERC, LVS, ESD analysis and defining analog / digital interface • You will work with EDA Vendors to proactively review latest tools and flows offerings in Physical Implementation domains, Evaluate latest offerings and benchmark with NXP used tools, flows and methodologies.
  • Needs to drive decision for next set of selections.
  • Work with EDA Vendors to review and resolve blocking issues. • You will ensure the compliance of your deliveries to NXP design flow, methodologies and quality standards (ISO 9001, ISO 26262 and CMMI). • You will be an actor of change for deploying new tools.
  • Specific skills & knowledge • Bachelor or Master in Electronics Engineering and specialization in VLSI domain. • 5-8 years of hands-on experience in SoC and IP level Synthesis, UPF, formal verification, floor plan, power plan, IO ring, Place & Route, DRC, ERC, LVS, ESD analysis and defining analog / digital interface •Scope of the work would cover STA flow/methodology development, continuous efficiency improvement, Flow development/Support for ECO convergence with tools in STA and ECO domain (PrimeTime, Tempus, Tweaker, PrimeClosure to name a few) • Proven experience in delivering physical implementation closure methodology of mixed signal SoC with high speed PHYs, IOs, PMU IP etc. closing analog / digital interfaces timing & signal integrity issues • Experience in Cadence tools, low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project • Experience in customizing flows & methodology to meet low power & area objectives of SoC and leading team to execute on time • Ability to use scripting languages / automation of Physical Implementation methodology creation and deployment • Should have proven experience in demonstrating strong technical leadership to deliver on commitment, anticipation of challenges, assertive communication and excellent team player. • Excellent communication skills with proven experience in international relationships More information about NXP in India... #LI-29f4

Tools & Skills

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Specialisation
Salary range
₹5-11 LPA to ₹38-65 LPA
Open roles at NXP Semiconductors
804 positions
Job ID
/job/Noida/Physical-Design-engineer_R-10063717-1

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