PDK Deck Developer

What You'll Do

• Physical Verification team is responsible for development of Calibre physical verification decks for cmos, FinFET, bulk, SOI, RF, bicmos and powermos technologies including DRC, LVS, PERC, Fill LPE, and shape generation decks and scripts.
• Development and validation of PV tools and flows using LLM based AI tools, recent EDA AI tools like Calibre AI, Virtuoso AI etc.
• Development of the Process Design Kit (PDK) infrastructure for PV tools, flows and utilities which includes setups, configurations, integration of technology specific data.
• Responsibilities will include testing, validation, customer support and new tool/methods evaluations, development of methods and procedures for quality improvement, automation of deck/techFiles generation and validation.
• Job Qualifications Required experience (15+ yrs) with PDK Physical Verification rule deck development/support and/or support of (1) Physical verification rule decks/runsets - DRC/LVS/ERC/PERC/FILL Or (2) Parasitic and EMIR rule decks In depth knowledge of foundry based and EDA tools based process variation formats e.g.
• ICT, IRCX etc. and understands latest EMIR & EM challenges.
• Experience with either - Calibre SVRF/TVF rule deck coding OR Cadence PVS/Assura rule deck coding is a must.
• Experience with some of the following tools is required: Calibre, CalibreXRC, Assura, Assura RF, Cadence PVS, Synopsys ICV, Virtuoso, Cadence QRC, StarRCXT, Voltus, Redhawk.
• Experience with at least 2 of the following programming languages is a plus: perl, python, skill, shell, c/c++, tcl.
• BE/B.Tech/ME/M.Tech in Electrical or Electronics Engineering or other similar discipline with at least 15+ years of relevant experience More information about NXP in India... #LI-7013