Lead Standard cell design/characterization Engineer

Qualifications

• Experience in Standard Cell Circuit design, Characterization and/or Layout design of various Standard cells and Macros (viz. flip flops, latches, multibit flip flops, level shifters, Power Switch Cells, Retention flops, Synchronizer cells etc.) in planer and non-planar technology nodes.
• At least 7-9 years of experience in StdCell domain AIML/Agentic AI literacy Work involved is Characterization, Layout design and EDA development of StdCells.
• Overview and good understanding of Circuit and MC simulations, Layout Dependent Effects and overall RTL2GDS flow (STA, PnR).
• Good understanding of CMOS and FinFET technologies.
• Good understanding and expertize in using of State-of-the-art EDA tools from Siemens, Cadence and Synopsys for simulations, characterization, and layout developments.
• Contribute in the improvement/development of circuit design, Characterization of StdCell libraries.
• Implement Innovative solutions within Standard cell library development domain.
• Develop EDA views including Characterization of NLDM, CCSP.
• CCSN and AOCV, LVF for standard cell libraries Exposure to AOCV, LVF model characterization is plus.
• Working knowledge in MS Excel, PowerBI and/or Tableau could be an added advantage.
• Working Knowledge of SKILL / Python / TCL / PERL scripting could be an added advantage.
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