Lead STA Engineer

What You'll Do

• Constraint Development: Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes.
• Timing Signoff: Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations.
• Violation Debugging: Debug and resolve setup, hold, transition, and path-based violations (PBA).
• Optimization & ECO: Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs).
• Cross-functional Collaboration: Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models.
• Tool & Flow Automation: Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools and improve script-based automation.
• Drive a small team of STA engineers.
• Should be able to do IP level synthesis.
• More information about NXP in India... #LI-7013