Lead Physical Design Engineer

What You'll Do

• Execute block & Chip level physical design from synthesized netlist to GDSII: Floorplanning and power grid design Placement and optimization Clock Tree Synthesis (CTS) Routing and post-route optimization Drive timing convergence across MCMM scenarios in collaboration with STA teams Ensure design closure including: Setup/hold timing closure DRC/LVS clean signoff IR drop and electromigration (EM) compliance Debug and resolve: Congestion issues SI/crosstalk problems Functional and physical ECOs Collaborate cross-functionally with: RTL/design teams to improve QoR DFT teams for test readiness Packaging and full-chip integration teams Contribute to methodology improvements and automation through scripting Follow and enforce NXP design methodologies, quality and reliability standards Required Qualifications Bachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics 8 - 10 years of experience in ASIC Physical Design More information about NXP in India... #LI-9415