Lead PERC Rule Deck Development Engineer

What You'll Do

• As the Lead PERC Rule Developer for the NXP Design Enablement Department, you will own and drive PERC rule development and methodology enablement for complex design verification use cases.
• Key responsibilities include: Lead development, enhancement, validation, and release of Calibre PERC rule decks for ESD, latch-up, power-domain, connectivity, and reliability verification requirements.
• Translate technology, product, and design signoff requirements into scalable, maintainable PERC checks and reusable verification methodologies.
• Drive PERC flow enablement across IP, block, subsystem, and SoC design stages, ensuring consistent integration with LVS, extraction, and overall physical verification signoff flows.
• Debug complex PERC/LVS issues in collaboration with design, layout, CAD, and technology teams; provide clear root-cause analysis and actionable closure recommendations.
• Develop automation scripts, regression suites, quality checks, and reporting utilities to improve rule development efficiency, release quality, and traceability.
• Partner with analog, AMS, CAD, product, and technology stakeholders to define verification requirements, acceptance criteria, and deployment plans for new or enhanced checks.
• Establish best practices for rule coding, validation, test-case creation, documentation, version control, and release readiness.
• Support design teams during key milestones such as IP readiness, MPW/FDIP development, tapeout preparation, and customer signoff readiness.
• Monitor rule deck quality, resolve priority issues, and provide timely status reporting to stakeholders and management.
• Mentor junior engineers and help build PERC, ESD, and physical verification competency within the team.
• Preferred / Additional Experience Exposure to AMS verification, reliability verification, or custom analog signoff flows.
• Hands-on experience with transistor-level extraction, post-layout verification, or RC-aware debug.
• Experience defining methodology roadmaps, reusable verification platforms, or productivity automation for large design organizations.
• More information about NXP in India... #LI-2734