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What You'll Do
- DfT Strategy & Architecture Define the overall DfT strategy for SoCs and IPs.
- Establish digital, memory and analog DfT architectures.
- Create and maintain the DfT Specification.
- Define testability requirements and acceptance criteria.
- Drive architectural decisions balancing quality, cost, test time and schedule.
- Assess test impact of specification and design changes.
- Technical Leadership Act as technical lead for DfT implementation teams.
- Drive alignment between architects, designers, verification engineers and product engineers.
- Review designs for compliance with DfT requirements.
- Resolve complex technical issues and architectural trade-offs.
- Lead DfT reviews throughout the product lifecycle.
- Test Quality & Production Readiness Define test concepts required to achieve target quality levels.
- Guide fault modelling and coverage strategy.
- Support prediction of yield, DPPM, test coverage and test cost.
- Support silicon bring-up, characterization and production ramp.
- Drive root-cause analysis of field and production failures.
- Methodology & Innovation Develop and deploy new DfT methodologies.
- Drive standardization and reuse across projects and business lines.
- Influence EDA tool roadmaps and automation improvements.
- Participate in internal and external technical working groups.
- Monitor industry trends and introduce best practices.
- Competence Development Coach DfT engineers and emerging architects.
- Build organizational competence through training and mentoring.
- Contribute to hiring and technical career development.
- Serve as a recognized expert within NXP and externally.
- Qualifications MSc or PhD in Electrical Engineering, Computer Engineering or related discipline.
- Experience 1 5 + years of experience in semiconductor development.
- Proven experience as DfT Architect, Lead Engineer or Technical Lead.
- Track record delivering complex SoC products from concept through production.
- Technical Expertise Strong knowledge of: Scan architecture and ATPG / Test compression / JTAG / IEEE1687 / JTAG / IEEE1149.x Memory BIST / Logic BIST Analog DfT and mixed-signal test Fault modelling and coverage analysis / Silicon debug and diagnosis Production test development Automotive quality methodologies RTL design and verification flows Modern EDA tools (Synopsys, Cadence, Siemens.
- Leadership Competencies Strategic thinking Systems perspective Technical influencing Stakeholder management Coaching and mentoring Change leadership Excellent communication skills More information about NXP in the Netherlands... #LI-c856
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Salary range
₹5-10 LPA to ₹35-58 LPA
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775 positions
Job ID
/job/Nijmegen/DfT-Architect_R-10064267-1
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