Senior VLSI Integration Engineer

Overview

• The complexity of the chip has greatly increased over the years.
• We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment.
• The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification.
• You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
• In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.
• What you'll be doing: Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
• Be exposed and work on a variety of functional and structural challenges.
• Including functional debug, physical design readiness, emulation, resolve design quality issues.
• Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks Taking part in flows development and deployment What we need to see: B.SC./ M.SC.
• in Electrical Engineering/Computer Engineering.
• 7+ years of actual design experience in chip design Solid hands-on RTL design skills in System-Verilog Proficiency in at least one scripting languages like python, bash, tcl.
• Way to stand out from the crowd : Passion for quality.
• Experience with delivery to physical design, emulation, firmware and other customers NVIDIA has some of the most forward-thinking people in the world working for us.
• Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid.