Senior Silicon Validation Methodology Engineer - Low Power

Overview

• NVIDIA Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional team at NVIDIA.
• We sit at the crossroads of design, architecture, marketing, operations, and productization.
• Our contributions span from the architecture stage through final product definition.
• We architect solutions for Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets.
• We are fast-paced, collaborative, and focused on making groundbreaking, impactful products.
• We are seeking a Senior Silicon Validation Methodology Engineer for Low-Power (LPWR).
• You will own the department LPWR validation methodology across GPU, SoC, and CPU, from architecture to silicon to product.
• What you'll be doing: Own architecture, design, and first-use of end-to-end LPWR validation methodology from silicon to product, covering corners, edge conditions, variability, and real-world scenarios.
• Set the department standard for LPWR validation so it is reused across a broad array of silicon products.
• Define what needs to be tested, why, and how — including coverage bounds, PVT/variability, test-time vs.
• schedule, signoff criteria, milestone playbooks, and SOL(speed of light) expectations.
• Invent and land new LPWR validation approaches that go beyond extending an existing test plan.
• Challenge current paradigms on performance, power, idle vs.
• active behavior, and corner-case coverage, and drive the resulting methods, tools, and metrics into org default practice.
• Set LPWR validation strategy and policy across teams, including long-lead items that outlive a single execution cycle.
• Translate architecture and product goals into multi-generation methodology, infrastructure, and tool investments.
• Drive cross-functional consensus with Architecture, Design, Firmware, and Software under conflicting PPA, coverage, latency, and schedule priorities.
• Improve validation workflow at department scale by building and adopting automation, coverage metrics, pre-silicon to post-silicon correlation, and AI-enabled analysis.
• Fold learnings back into methodology, spec, and design.
• What we need to see: A Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
• 8+ years of hands-on silicon validation methodology experience, with deep ownership of low-power architecture and design (idle power, power gating, clocking, DVFS, and related features) and silicon features tied to current energy-efficient design.
• Proven record of creating new LPWR validation methods, tools, or signoff criteria that were adopted across multiple products or teams.
• Expert debug of silicon LPWR issues, and the ability to deconstruct ambiguous failures into simpler, reusable validation and corrective approaches that raise quality and efficiency for the org.
• Demonstrated strong ability to set validation strategy under hard trade-offs: functionality vs.
• performance/power, latency vs.
• coverage, and coverage vs.
• Strong collaboration skills and Proven track record of influencing and leading cross-functional/group(design, Board, FW, SW) consensus through product launches in low-power domains.
• Strong AI-enabled skills and thinking — use AI to accelerate analysis, exploration, and documentation while maintaining rigor, originality, and judgment that do not come from AI.
• Ways to stand out from the crowd: Set LPWR or power-management validation policy, playbooks, or signoff bars that other teams ran without you in the critical path.
• Have shipped methodology reuse across multiple chips, SKUs, or platforms, with measurable impact such as higher coverage, fewer debug loops, lower SOL, or faster bring-up.
• If you are energized by owning a domain, setting the bar for others, and turning low-power silicon expertise into reusable methodology at NVIDIA scale, we'd love to talk to you.