Senior Physical Methodology Design Engineer

Overview

• NVIDIA has continuously reinvented itself.
• Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing.
• Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.
• NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world.
• This is our life's work, to amplify human creativity and intelligence.
• As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.
• Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs.
• This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
• We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
• What you'll be doing: In this position, you will expected to be part of the physical design methodology team.
• PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EMIR DROP, DRCs & schematic to layout verification.
• Work in collaboration with design team for addressing design challenges.
• Help team members in debugging tool/design related issues.
• Constantly look for improvement in RTL2GDS flow to improve PPA.
• Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
• Write scripts (TCL/Python) to help design teams move forward with their design and chip goals Build flows based on industry standard EDA tools to implement designs efficiently and improve PPA.
• Support flows for chip design teams across tapeouts and tech nodes.
• What we need to see: BE/BTECH/MTECH, or equivalent experience.
• 3+ years of experience in Physical Design, preferably with methodology/flow experience.
• Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies.
• Good understanding of the RTL2GDSIl concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
• Expertise on high frequency design methodologies.
• Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification.
• Working experience with tools like ICC2/Innovus, Primetime/Tempus/Seahawk etc used in the RTL2GDSIl implementation.
• Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred.
• Well versed with timing constraints, STA, IR and ECO timing closure.
• Strong algorithmic thinking with good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
• Python will be helpful too.
• Ability to multi-task and flexibility to work in global environment.
• Good communication skills and strong motivation, Strong analytical & Problem Solving skills Willingness to learn and master new techniques quickly Innovate and drive changes across teams & workflows #LI-Hybrid.