Senior Chip Design Verification Engineer

Overview

• We are now looking for a Chip Design Verification Engineer.
• NVIDIA is seeking a verification engineer to join the chip design methodologies team.
• The team is in charge of the verification methodologies, shared code, training, and embracing new technologies.
• One of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries.
• This position offers the opportunity to have real impact in a dynamic, technology-focused company.
• What you'll be doing: Develop shared verification code and solutions to be widely used by the chip design team.
• Develop groundbreaking methodologies to create a flawless experience for verification engineers to keep the focus on new problems.
• Collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
• Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our verification process.
• Understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Collaborate with designers, verification specialists to accomplish your tasks.
• Develop training sessions.
• What we need to see: A Bachelors Degree in Electrical Engineering or Computer Science.
• Exposure to design and verification tools.
• 5+ years of hands-on pre-silicon verification experience.
• Strong interpersonal skills and ability & desire to innovate.
• Ways to stand out from the crowd: Experience in Specman / SystemVerilog UVM.
• Understanding simulation tools.
• Experience in building test benches, evaluate coverage and debug simulation failures.
• NVIDIA has some of the most forward-thinking and hardworking people in the world working for us.
• Are you a creative and autonomous engineer who loves a challenge? Come join our networking verification team and help us developing great products by raising the efficiency and the quality standard in our chip design team.