High Speed IO Validation Engineer

Overview

• NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years.
• Today, we are tapping into the unlimited potential of AI to define the next era of computing — an era in which our GPUs act as the brains of computers, robots, and self-driving cars that understand the world.
• Doing what has never been done before takes vision, innovation, and the world’s best talent.
• NVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production.
• We are hiring an HSIO Validation Engineer to own characterization and qualification of high-speed I/Os — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet — on brand-new silicon serving datacenter, AI, and client markets.
• Your bench is where silicon meets the signal — where every link train, jitter sweep, eye diagram, and protocol corner gets exercised before the part ships.
• You drive characterization and debug for IO interconnects across silicon, board, firmware, and driver — designing tests that anticipate rack-scale deployment so marginality surfaces at die-and-board scale, never in a rack.
• Your decisions show up in link margin, BER, power per lane, and the go/no-go calls that gate samples and production.
• What you will be doing: Own end-to-end characterization and validation of high-speed IO — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet — from silicon die through package and board, on NVIDIA GPUs, CPUs, and SoCs.
• Develop and execute validation test plans for silicon and SoC-level HSIO features — bring-up, corner qualification, stress, productization, and structured DOE across PVT, board, cable/connector, thermal, and firmware variables — left-shifting silicon failures before deployment.
• Drive power characterization and optimization across IO interconnects under workload-representative stimuli (MLPerf-class patterns at silicon/board level) — analyze trade-offs across V/F, lane config, and protocol state — and feed back into design, firmware, and binning.
• Drive systematic root-cause analysis for complex HSIO bugs — isolating contributions across silicon, package, board, firmware, and driver, with platform/thermal/mechanical partners when system context matters.
• Convert rack-observed failures into silicon/board reproducers so future spins fix the root cause upstream.
• Assess manufacturing and yield implications of HSIO margin distributions — identify gaps in scaling from chip to product, and feed back into binning and design.
• Develop and improve validation methodologies, automation frameworks, and margin-tracking infrastructure — increase efficiency and coverage as platform complexity grows.
• What we need to see: BS or MS in Electrical or Computer Engineering (or equivalent), with 8+ years in post-silicon HSIO validation, characterization, or a closely related discipline.
• Deep understanding of high-speed serial link protocols (PCIe Gen5+, NVLink, NVLink-C2C, UCIe, CXL) and the underlying SERDES architecture — equalization, link training, electrical characterization — with strong signal integrity and jitter knowledge.
• Strong SI and PI fundamentals — S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, jitter decomposition — and validation experience across silicon and platform boundaries (CoWoS/interposer/substrate, board), translating rack-environment effects into silicon/board characterization.
• Hands-on with lab instrumentation (DSOs, BERTs, VNAs, protocol/logic analyzers, TDR), DOE/shmoo/margin-trending, and Python-based test automation — with a track record of driving cross-functional debug across chip, package, board, firmware, driver, and system teams.
• Ways to stand out from the crowd: Hands-on experience with PCIe Gen5/Gen6 or NVLink validation on production silicon — link training, equalization tuning, BER margining, or compliance debug.
• Prior SERDES, mixed-signal, or analog circuit design experience — sufficient to independently form hypotheses, design Sim-to-Si correlation experiments, and propose silicon/system-side fixes during debug.
• Track record of translating rack-environment conditions (thermal, connector reliability, neighbor noise) into silicon/board characterization — finding marginality at die-and-board scale before it appears in the field.
• Comfortable using AI productivity tools (Claude, Copilot, or equivalent) to compress log triage, regression analysis, scripting, and reporting workflows.