Dataflow Development Engineer - LPU Hardware DataFlow

Overview

• NVIDIA is known as the "AI Computing Company." Our GPUs power modern Deep Learning software frameworks, accelerated analytics, data centers, and autonomous vehicles.
• We are looking for a Dataflow Development Engineer - LPU Hardware to join our team and develop, build, and improve dataflow systems at the hardware–software boundary.
• You will work on FPGA accelerator dataflow: implementing and tuning dataflow pipelines, creating host-side drivers and runtimes that collaborate with programmable logic, and jointly inventing hardware and software for deterministic, low-latency execution.
• Dataflow development engineers at NVIDIA connect FPGA and custom hardware with our software systems.
• You will implement dataflow graphs and streaming pipelines in hardware.
• You will build efficient host–device interfaces (PCIe, DMA, VFIO) and collaborate with compiler and architecture teams to map high-level dataflow onto FPGA and accelerator fabrics.
• Your work directly affects latency, efficiency, and resource usage for inference at scale.
• The ideal candidate has a proven hardware approach, including experience with FPGA development, HDL, or hardware/software co-design.
• They can analyze timing, resource usage, and data movement.
• We seek engineers comfortable working from RTL to runtime.
• They consider pipelines and hardware performance and enjoy implementing dataflow architectures in silicon and programmable logic.
• What you'll be doing: Build and implement dataflow pipelines and streaming architectures in FPGA or programmable logic.
• Develop host-side software, drivers, and runtimes that collaborate with FPGA and accelerator hardware (e.g.
• Partner with compiler and hardware groups to allocate dataflow graphs onto hardware resources; improve latency, processing efficiency, and area/utilization.
• Build and maintain hardware–software co-design flows: from high-level dataflow specs to synthesis, place-and-route, and validation.
• Build tooling and methodologies for debugging, profiling, and validating dataflow behavior in hardware; participate in design reviews and cross-team alignment across EMEA and globally.
• What we need to see: BS or higher degree or equivalent experience in CS/EE/CE with more than 5 years in FPGA development, hardware dataflow, or hardware/software co-design.
• Hands-on experience with RTL/HDL (Verilog, VHDL) or high-level synthesis (HLS); ability to build and debug dataflow-style pipelines in hardware.
• Solid programming abilities in C/C++ for host drivers, runtimes, or tooling; familiarity with hardware interfaces (e.g.
• PCIe, DMA, memory-mapped I/O).
• Proven understanding of dataflow and streaming concepts: pipelining, backpressure, buffering, and resource/area trade-offs.
• Familiarity with FPGA toolchains (synthesis, P&R, timing closure) and with Linux, scripting, and version control.
• Excellent communication in English; ability to work with distributed teams.
• Ways to stand out from the crowd: Experience working with FPGA dataflow for machine learning inference, networking, or high-throughput streaming (e.g.
• Xilinx/AMD, Intel FPGA).
• VFIO, SR-IOV, or other pass through/virtualization for accelerators; low-level driver or BSP development.
• ASIC or custom-silicon dataflow build; RTL develop for dataflow or network-on-chip (NoC).
• Background in compiler backends or HLS that targets FPGAs; MLIR or IR-level optimization for hardware mapping.
• Experience with multi-FPGA or FPGA–GPU systems; distributed dataflow across programmable logic and accelerators.
• Join our team of world-class engineers and be part of the groundbreaking work we do at NVIDIA.
• We are committed to encouraging a collaborative and inclusive environment, where every team member has the opportunity to thrive and make a significant impact!.