ASIC Verification Engineer - PMU

Overview

• As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing.
• Our PMU IP, developed over the past 17 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios.
• The PMU IP consists of a RISC-V core and custom-designed control logic.
• It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points.
• We are seeking a Senior Verification Engineer to join our Power Management Unit (PMU) IP team to help building more powerful PMU engine.
• What you’ll be doing: Co-work with the IP architect and designer to define the IP verification methodology and test plan.
• Finishing the IP verification for all new coming features from project to project.
• Maintain and improve the UVM based unit-level TB to be powerful and efficient.
• Maintain the regression and run various of sing-off verification checklists.
• Learn and practice formal verification, and use formal tool to assist simulation to raise the verification quality.
• What we need to see: BS with 4+ years of experience or MS with 2+ years of working experience.
• Self-driving, active thinking and problem solving.
• Experienced with SystemVerilog and UVM methodology.
• Familiar with perl or python script.
• Familiar with C/C++ coding.
• Fluent oral and written English.
• Ways to stand out from the crowd: Have the experience of building a complex TB from scratch.
• Good at solving environment issues.
• Like setting up Makefile, solving VCS issue, or solving issues brought by tool updates, etc.
• Good communication skills.
• State problem clearly.