ASIC Physical Design Engineer

Overview

• ASIC-PD team is hiring engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow.
• Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.
• What you'll be doing: STA for hierarchical design.
• Constraints creation and validation, timing budget.
• Timing closure for both partition and full chip level.
• Special timing closure, such as io, test, clock etc.
• Synthesis, Netlist quality check, Formal Verification.
• Implement chip partition and floorplan.
• Function eco creation.
• Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout).
• Flow automation development, Methodology in any of above areas.
• What we need to see: MS in EE, CS or Microelectronics with 1+ year is preferred Project experience in IC design implementation.
• Courses taken in circuit design, digital design Hand-on experience in EDA software from Synopsys (FC/DC/PT/Formality), Cadence (RC compiler/Genus/LEC) is helpful Proficient user of Python, perl or TCL is helpful Proficient in English reading and writing Ways to stand out from the crowd: Proficient user of Perl, Python or TCL is preferred.
• Excellent English communication skill.