ASIC Design Engineer

Requirements

• Bachelor’s degree with 4+ years of pre-silicon RTL design experience or Master’s degree in Electrical Engineering with 3+ years of experience.
• Experience developing RTL for complex digital IP from specification through implementation handoff.
• Hands-on experience with ASIC low-power methodologies including UPF-based power intent and CDC/RDC analysis.
• Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing analysis.
• Proficiency in Verilog/SystemVerilog and industry-standard simulation tools.
• Preferred Qualifications Hands-on experience with RTL and gate-level power analysis using tools such as Design Compiler and PrimeTime.
• Understanding of low-power design techniques including clock gating, power gating, and multi-voltage designs.
• Experience collaborating across RTL, verification, synthesis/STA, and physical design teams.
• Familiarity with CMOS digital and mixed-signal circuit concepts and their system-level trade-offs.
• Experience with memory or high-performance digital build is preferred.
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