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What You'll Do
- span the full front-end design flow — from architecture and specification through RTL development, integration, and design sign-off — in close collaboration with verification, physical design, and architecture teams.
- Define microarchitecture and develop Verilog/SystemVerilog RTL for SoC-level components, including interconnects, memory interfaces, and global logic such as reset, clocking, and power management.
- Collaborate with verification teams to review test plans, support functional debug, and help close coverage gaps during development.
- Run standard design checks such as lint and CDC/RDC, define timing constraints, and work with synthesis and physical design teams to ensure the design meets implementation requirements.
- Coordinate with IP teams to integrate complex interfaces and resolve subsystem-level issues.
- Contribute to design methodology, improve integration workflows, and provide technical guidance to other engineers.
- What We're Looking For To be successful in this role, you must: Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 8-12 years of related professional experience.
- Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
- Experience in Micro-architecture for complex Custom SoC/ASIC products.
- Excellent Logic design and debug skills.
- RTL design experience, Synthesis, static-timing closure, formal verification, gate-level simulations and block-level function verification.
- Design knowledge of one/more industry-standard bus protocols (AXI, AHB, APB) a plus.
- Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies is a must.
- Knowledge of scripting languages, such as Python Experience with highspeed, low power, and area optimized designs.
- Experience working with multi-clock designs, DFT, resets, LEC, Lint, etc.
- Expected Base Pay Range (USD) 135,900 - 201,130, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
- The expected base pay range for this role may be modified based on market conditions.
- Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
- Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
- Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
- We look forward to sharing more with you during the interview process.
- Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
- Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
- These tools must not be used to record, assist with, or enhance responses in any way.
- Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.
- Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
- This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
- As such, applicants must be eligible to access export-controlled information as defined under applicable law.
- Marvell may be required to obtain export licensing approval from the U.S.
- Department of Commerce and/or the U.S.
- Department of State.
- Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-JT2
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Salary range
₹5-12 LPA to ₹40-70 LPA
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/job/Boise-ID/Senior-Staff-RTL-Design-Engineer_2601967
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