Senior Staff Engineer - Design Verification- SerDes/PHY/AMS
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Salary range — Verification in India
Fresher (0-2y)
₹5-12 LPA
Mid (3-5y)
₹12-25 LPA
Senior (6-10y)
₹25-45 LPA
Staff (10+y)
₹40-70 LPA
Typical skills for Verification
UVMSystemVerilogFormal VerificationCoverage-Driven VerificationAssertionsEmulationPython/scripting
Common EDA tools
Synopsys VCSCadence XceliumSynopsys VerdiCadence JasperGoldSiemens Questa
About Verification roles
Validates chip designs using UVM/SystemVerilog methodologies, building constrained-random testbenches and achieving functional coverage closure
Market insight: Fastest-growing VLSI role in India. AI/ML chip complexity means 60-70% of design effort is verification. Formal verification and emulation skills are hot. Verification engineers outnumber RTL designers 2:1 at most companies.
Full description on Marvell Technology’s career page.
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Marvell Technology
108 positions
Job ID
/job/Bangalore/Senior-Staff-Engineer---Design-Verification---SerDes-PHY-AMS_2601686
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