Senior Staff Engineer, ASIC Design/Implementation -- LEC/STA/Power Analysis

What You'll Do

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for sta signoff.
• Own and contribute to various sta related tasks like doing timing ecos for blocks and SoCs, developing custom scripts to create histograms, sta flow management, etc.
• Perform static timing analysis (STA) using industry-standard tools (e.g.
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Resolve or find workarounds for tool issues, independently or working with EDA tool vendors.
• Conduct post-route timing checks and quality of results (QoR) analysis.
• Automate STA related processes/flow using scripting languages such as Tcl or Python.
• Create QoR dashboards, histograms for STA runs across all modes.
• Ensure compliance with timing signoff checklists and criteria.
• Document best practices and lessons learned to drive continuous improvements in future projects.
• What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
• Minimum of 5 years of industry experience in ASIC timing and sta.
• Strong understanding of ASIC design flows, from RTL to GDSII.
• Knowledge and hands-on experience with sta methodologies and implementation.
• Proficiency in using STA tools, and scripting languages (e.g., Tcl, Perl).
• Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
• Strong understanding of timing constraint development for hierarchical designs, timing ECO creation and final timing signoff.
• Familiarity with physical design and timing optimization techniques and strategies to achieve deterministic timing closure.
• Proven track record of delivering successful designs on time and meeting performance, power and area goals.
• Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues.
• Strong communication and collaboration skills to work effectively within cross-functional teams.
• Expected Base Pay Range (USD) 135,900 - 201,130, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
• The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
• Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
• Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
• We look forward to sharing more with you during the interview process.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
• Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• These tools must not be used to record, assist with, or enhance responses in any way.
• Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.
• Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
• This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
• As such, applicants must be eligible to access export-controlled information as defined under applicable law.
• Marvell may be required to obtain export licensing approval from the U.S.
• Department of Commerce and/or the U.S.
• Department of State.
• Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-NF1