Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity

What You'll Do

• Serve as the senior SI/PI technical authority for customer platforms built on Marvell's Ethernet switches and UALink silicon, from early channel definition through mass-production qualification.
• Define and maintain layout and routing guidelines for high-speed SerDes channels, power delivery networks, and sensitive analog interfaces — and drive their adoption with customers, ODMs, and internal teams.
• Perform post-silicon channel extraction, full-channel simulation, and what-if analysis on customer board designs, and recommend targeted layout and stack-up fixes that move designs from "passing" to "best-in-class margins." Lead compliance testing and lab characterization — BER/SER, eye-opening margins, jitter, return loss, crosstalk — and translate measurement data into actionable design and SerDes-tuning guidance.
• Provide SerDes tuning guidance to customers based on simulation results, lab measurements, and field telemetry; partner with Marvell silicon teams to refine tuning methodologies.
• Run and review power integrity simulations covering PDN impedance, IR drop, decoupling effectiveness, transient response, and droop, and guide customers on robust PDN architectures for high-current ASICs.
• Translate customer power needs and constraints into structured feedback for Marvell silicon, packaging, and platform engineering teams — closing the loop for continuous product improvement.
• Engage directly with ODMs on SI/PI guidance, design reviews, and qualification activities, partnering with the global Customer Solutions Group and internal engineering teams.
• Support definition and validation of reference designs for new Marvell silicon — owning the SI/PI side of the design from early channel budgeting through customer release.
• Provide hands-on lab debug expertise during customer bring-up and production ramp, using VNAs, BERTs, real-time scopes, TDR equipment, jitter analyzers, and compliance test kits.
• Develop and deliver SI/PI training to customers, ODMs, and internal Marvell teams — covering high-speed design best practices, simulation methodology, and lab debug techniques.
• Provide technical leadership on 112G and 224G PAM4 SerDes designs today, and help shape Marvell's SI/PI approach for next-generation 448G systems.
• Partner closely with Marvell Silicon Design, Packaging, Board/System HW, Software, and Operations teams to deliver fully integrated solutions.
• Contribute to product definition and roadmap planning by bringing real-world SI/PI insights into architecture and marketing discussions.
• Represent Marvell's SI/PI expertise in customer briefings, executive reviews, and industry technical forums.
• What We're Looking For PhD, Master's, or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 15+ years of experience in hardware design, development, and validation of high-speed networking or compute systems. 10+ years of focused experience in signal integrity and power integrity work on high-speed SerDes platforms (25G NRZ through 112G/224G PAM4).
• Demonstrated expertise across the full SI lifecycle: channel modeling and budgeting, layout and stack-up guideline definition, post-layout extraction and simulation, design-fix recommendations, and compliance/tuning guidance.
• Strong PI capability — able to independently run and review PDN simulations covering impedance, IR drop, decoupling, transient response, and droop, and translate results into customer guidance.
• Fluency across the leading SI/PI EDA toolchains (Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, or equivalent) — comfortable picking up and using whichever tools the project demands.
• Strong hands-on lab expertise: VNAs, BERTs, real-time and sampling oscilloscopes, TDR, jitter analyzers, and high-speed compliance test kits — with proven debug capability in customer and internal lab environments.
• Customer-facing experience supporting complex technical engagements and resolving real-world deployment issues.
• Proven ability to develop and deliver technical training content to engineering audiences.
• Excellent communication skills, with the ability to influence senior customer engineering teams, ODM engineers, and internal stakeholders across disciplines and geographies.
• Note on experience level: While the years of experience above represent the typical bar for this role, exceptionally talented candidates with fewer years but demonstrated mastery — through impactful project work, deep technical contributions, or industry recognition — are strongly encouraged to apply.
• Preferred Direct experience with Ethernet switch platforms (any tier) and/or emerging open AI fabric standards and architectures.
• Experience supporting SI/PI for platforms targeting megascale data center deployments at production volume.
• Background in reference platform SI/PI definition and customer enablement for silicon-based solutions.
• Familiarity with ODM/CM design and qualification flows, including DFM/DFT, reliability testing, and high-volume manufacturing variability.
• Experience defining SerDes tuning methodologies and correlating simulation, lab, and field-telemetry data.
• Familiarity with chip-to-module, copper cable, and connector ecosystems relevant to high-speed Ethernet and AI fabric channels.
• Track record of influencing silicon and platform roadmaps based on SI/PI insights from customer and field deployments.
• Leadership & Impact: As a senior technical leader within the Customer Solutions Group, you will: Set the SI/PI technical bar across Marvell's most strategic customer engagements, ensuring designs are not just compliant but production-robust.
• Serve as a key technical interface between customers, ODMs, Marvell silicon teams, and internal hardware engineering — accelerating learning in all directions.
• Mentor engineers across the team and lead SI/PI training for customers, ODMs, and internal stakeholders, raising collective expertise in high-speed design and validation.
• Shape the direction of Marvell's customer-facing hardware solutions and influence next-generation product evolution.
• Act as a technical ambassador, representing Marvell's hardware expertise to top-tier customers, ODM partners, and industry forums.
• Travel as needed to customer sites, ODMs, and labs — typically project-driven rather than continuous.
• Expected Base Pay Range (USD) 177,820 - 266,400, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
• The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
• Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
• Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
• We look forward to sharing more with you during the interview process.
• Any applicant who requires a reasonable accommodation duri