Senior Principal Engineer, Digital IC Design

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What You'll Do

  • but not limited to.
  • Improve the design methodology and flow.
  • RTL designs for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
  • Collaborate with Analog/DSP/DV/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
  • Provide the support to the product teams, for both pre and post silicon What We're Looking For MSEE with 10+ years of experience.
  • Good personal communication skills and team working spirit.
  • Hardworking and motivated to be part of a highly competent design team.
  • Must be proficient in the following skills: Fundamental concepts in digital logic design Understand ASIC verification flows and methodologies Verilog and SystemVerilog/SystemC/Vera Strong Perl and Tcl scripting UNIX Shell scripting (Csh, Bash) Highly desirable skills: Formal verification Low power design MATLAB and C/C++ based system simulation and evaluation DSP function hardware implementation knowledge #LI-TD1 Expected Base Pay Range (USD) 182,360 - 273,200, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
  • The expected base pay range for this role may be modified based on market conditions.
  • Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
  • Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
  • Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
  • We look forward to sharing more with you during the interview process.
  • Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
  • Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
  • These tools must not be used to record, assist with, or enhance responses in any way.
  • Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.
  • Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
  • This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
  • As such, applicants must be eligible to access export-controlled information as defined under applicable law.
  • Marvell may be required to obtain export licensing approval from the U.S.
  • Department of Commerce and/or the U.S.
  • Department of State.
  • Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-VP1

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Marvell Technology

Santa Clara, CA

Specialisation
Open roles at Marvell Technology
538 positions
Job ID
/job/Santa-Clara-CA/Senior-Principal-Engineer--Digital-IC-Design_2600387-1

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