Principal, Emulation Engineer

About the Team

• The Connectivity Business Unit at Marvell is at the forefront of delivering high-performance silicon for the world's most demanding data infrastructure, spanning Optical DSPs, PCIe/CXL retimers, high-speed Ethernet PHYs, and AEC/AOC enablement devices.
• Within the BU, the Pre-Silicon Emulation team plays a critical role in program execution—bridging RTL design and real-world system behavior before a single chip is taped out.
• Our team owns emulation model development, test execution, and system-level debug across Marvell's emulation platforms (Palladium, Veloce, Zebu), enabling early firmware bring-up, hardware/software co-validation, and risk reduction on the path to silicon.
• We work closely with design, verification, firmware, software, and post-silicon teams to ensure emulation is a productive, schedule-driving resource—not a bottleneck.
• If you thrive on solving complex technical problems at the intersection of hardware and software, and want your work to directly impact the success of next-generation connectivity silicon, we'd love to hear from you.
• What You Can Expect What You Can Expect Execute emulation model bring-up, test development, and debug for connectivity silicon programs, including ODSP, PCIe/CXL retimers, high-speed Ethernet PHYs, and AEC/AOC enablement devices, on platforms such as Palladium, Veloce, and Zebu.
• Work with design, validation, and firmware teams to understand emulation hardware and software requirements, and implement platform configurations, transactors, speed bridges, protocol adapters, and firmware/software stacks.
• Engage with EDA and emulation hardware vendors to resolve platform, tooling, and model issues and maintain a productive emulation environment.
• Develop and maintain HW/SW enablement flows and scripts to support RTL validation and improve emulation model usability for firmware, driver, and system software development.
• Collaborate with pre-silicon validation, design, firmware, and post-silicon teams to identify and resolve emulation bottlenecks and improve validation coverage.
• Build and maintain automation scripts and infrastructure to improve emulation environment productivity, reliability, and utilization within assigned programs.
• What We're Looking For What We're Looking For Minimum Requirements Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 7+ years of relevant experience, or a Master's/PhD with 3+ years of experience.
• Hands-on experience with one or more SoC emulation platforms (Palladium, Veloce, Zebu), including building and maintaining emulation models for SoC designs.
• Background in test planning, simulation, and debug in Verilog/SystemVerilog environments.
• Experience with SoC development flows, emulation-based debug, and system-level validation.
• Scripting and automation skills using Python, Perl, Tcl, and/or UNIX shell.
• Ability to collaborate effectively with cross-functional teams including design, validation, firmware, and vendor partners.
• Good to Have Experience with emulation of networking devices or mixed-signal designs, including systems containing PHY or Layer-2/Layer-3 functionality.
• Exposure to connectivity-focused silicon, such as: Optical DSPs (ODSP) PCIe/CXL retimers High-speed Ethernet PHYs AEC/AOC enablement devices Familiarity with firmware or software bring-up using emulation platforms.
• Experience contributing to or improving emulation infrastructure within a project or product line.
• Expected Base Pay Range (USD) 150,680 - 225,700, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
• The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
• Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
• Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
• We look forward to sharing more with you during the interview process.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
• Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• These tools must not be used to record, assist with, or enhance responses in any way.
• Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.
• Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
• This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
• As such, applicants must be eligible to access export-controlled information as defined under applicable law.
• Marvell may be required to obtain export licensing approval from the U.S.
• Department of Commerce and/or the U.S.
• Department of State.
• Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-JT2