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Nice to Have
- Experience with formal verification tools and methodologies including connectivity checking, property verification, and equivalence checking Hands-on experience developing verification infrastructure for custom silicon, AI accelerators, or high-performance compute platforms Familiarity with advanced verification techniques including emulation/FPGA prototyping, hardware-software co-verification, and post-silicon validation support Knowledge of low-power verification methodologies including UPF (Unified Power Format) and power-aware simulation techniques Proficiency in C/C++ programming for verification infrastructure development, reference model creation, and integration with DPI-based testbench components Background in high-speed interface verification including 112G+ SerDes, PCIe Gen 6/7, CXL 3.0, or custom die-to-die interconnects Experience with memory subsystem verification including HBM, DDR/LPDDR controllers, or custom memory architectures Familiarity with verification metrics tracking, regression management systems, and continuous integration flows for large-scale SoC projects Experience mentoring junior verification engineers and contributing to verification methodology development Participation in customer-facing technical discussions and design reviews for custom ASIC development Expected Base Pay Range (USD) 0 - 0, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
- The expected base pay range for this role may be modified based on market conditions.
- Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
- Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
- Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
- We look forward to sharing more with you during the interview process.
- Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
- Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
- These tools must not be used to record, assist with, or enhance responses in any way.
- Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.
- Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
- This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
- As such, applicants must be eligible to access export-controlled information as defined under applicable law.
- Marvell may be required to obtain export licensing approval from the U.S.
- Department of Commerce and/or the U.S.
- Department of State.
- Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a
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₹5-12 LPA to ₹40-70 LPA
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503 positions
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/job/Boise-ID/Principal-Design-Verification-Engineer_2601014
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