Opens marvell.wd1.myworkdayjobs.com in a new tab
Qualifications
- Experience on end-to-end PCIe/CXL subsystem RTL design execution and sign-off Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms Proficient in debugging functional and performance issues at subsystem and SoC levels Familiarity with post-silicon bring-up and debug methodologies in collaboration with firmware and validation teams Prior experience mentoring engineers and providing technical leadership in a cross-functional environment Expected Base Pay Range (USD) 160,400 - 237,320, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
- The expected base pay range for this role may be modified based on market conditions.
- Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
- Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
- Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
- We look forward to sharing more with you during the interview process.
- Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
- Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
- These tools must not be used to record, assist with, or enhance responses in any way.
- Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.
- Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
- This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
- As such, applicants must be eligible to access export-controlled information as defined under applicable law.
- Marvell may be required to obtain export licensing approval from the U.S.
- Department of Commerce and/or the U.S.
- Department of State.
- Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AR3
Tools & Skills
Languages
Sourced directly from Marvell Technology’s career page
Your application goes straight to Marvell Technology.
Opens marvell.wd1.myworkdayjobs.com in a new tab
Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Marvell Technology
520 positions
Job ID
/job/San-Diego-CA/Principal-COE-Digital-Design-Engineer_2602413
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — freeSimilar RTL Design roles
NXP Semiconductors
Junior Digital Design Engineer - MCU
Catania|RTL Design
Micron Technology
Principal Engineer, High‑Speed RTL Design
Bengaluru, India|RTL Design
Micron Technology
MTS, AI Optimized Memory Digital Design Engineer
2 Locations|RTL Design
Intel
SoC Logic Design Engineer
US, Massachusetts, Beaver Brook|RTL Design