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What You'll Do
- Become a member of a world‐class design team.
- You will have an opportunity to design the latest high‐performance AI silicon and other critical high speed interface (PCIe, CXL, UA link) IP designs for Marvell’s core products.
- All team members participate in circuit architecture, RTL implementation, design review, layout, and silicon DV and validation in the following areas: Develop next generation silicon IP utilizing advanced digital technologies.
- Perform architecture discussion and design.
- Review architecture and define test plan, including RTL coding and debug.
- Support firmware team to develop production firmware code.
- Support validation team and FAE to trouble shoot for our silicon to find root cause and provide fix.
- Review design documentation, description and information to internal and external customers.
- What We're Looking For Requirements: Minimum BSEE plus 1~3 years of design experience in one of the following areas below: Analyze and improve design architecture and block-level IP microarchitecture Implement RTL design with Hardware Description Language (Verilog, SystemVerilog) On-Chip bus protocols knowledge: AXI, AHB, APB Performing Lint, CDC check, Timing closure, coverage closure analysis Basic understanding of UVM based test bench Basic understanding of scripting/programming language with PERL/Python, TCL and C/C++ Preferred: Knowledge in PCIe, NVMe, CXL, UAlink and implementations is a plus Additional Compensation and Benefit Elements Competitive salary, plus 13th-month salary and performance-based bonus RSUs (Restricted Stock Units) for new joiners and on-going annually Premium health & accident insurance for you and your family (spouse and children) Annual medical check-up at a designated hospital arranged by Marvell Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more.
- Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
- These tools must not be used to record, assist with, or enhance responses in any way.
- Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.
- Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
- This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
- As such, applicants must be eligible to access export-controlled information as defined under applicable law.
- Marvell may be required to obtain export licensing approval from the U.S.
- Department of Commerce and/or the U.S.
- Department of State.
- Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-UN1
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Specialisation
Open roles at Marvell Technology
503 positions
Job ID
/job/Ho-Chi-Minh/Digital-IC-Design--Senior-to-Staff-Engineer-_2600338
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