System Modelling Engineer

About This Role

• The Role and Impact: As an Analog and Mixed Signal IP Architect, you will play a pivotal role in shaping the future of Intel's cutting-edge technologies.
• You will be responsible for driving innovative architectures and algorithms that define the next generation of System-on-Chip (SoC) independent analog and mixed signal IPs.
• We are seeking an experienced SerDes PHY System Modeling Engineer to lead and support the architecture, modeling, and performance analysis of 224Gbps SerDes IP.
• This role focuses on endtoend PHY system modeling, including electrical channel, transmitter (TX), receiver (RX), equalization strategies, clocking, and jitter/noise analysis, enabling robust silicon implementation for nextgeneration ASICs and SoCs.
• Key Responsibilities: System Architecture and Modeling: Develop endtoend behavioral models for 224Gbps SerDes PHYs across TX, channel, and RX.
• Build statistical and timedomain system models to evaluate BER, eye margins, and link robustness Define PHY performance budgets (jitter, noise, ISI, crosstalk, insertion loss) Model and optimize PAM4 signaling at very high data rates Channel and Equalization Analysis: Model electrical channels including packages, PCBs, connectors, and crosstalk.
• Develop and tune TX FIR, RX CTLE, DFE, and adaptive equalization algorithms Perform Swept channel analysis to ensure compliance across worstcase conditions Support cooptimization of channel, package, and PHY architecture Clocking, Jitter and Noise Analysis: Model PLL/DLL behavior, phase noise, and jitter transfer functions Perform jitter decomposition (RJ, DJ, PJ, SJ) and bathtub curve analysis Analyze CDR performance, loop dynamics, and tolerance to jitter/noise sources Compliance and Standards Support: Support modeling and interpretation of industry standards (IEEE, OIF, etc.), including 224Grelated efforts Define channel and compliance test methodologies Align system models with compliance test specifications and silicon validation strategies Work closely with circuit designers, DSP/algorithm teams, package/PCB engineers, and validation teams Translate systemlevel requirements into blocklevel and circuitlevel specs Support silicon bringup and debug through correlation of lab data with system models Qualifications: Minimum Qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field, and 12+ years of relevant experience; or Master's degree and 8+ years of relevant experience; or PhD and 4+ years of relevant experience. - Proficiency in analog circuit design, including TX/RX blocks and system-level understanding. - Expertise in architecture modeling and high-speed design techniques. - Demonstrated ability to model, simulate, and optimize performance, power, and area for analog and mixed signal IPs.