Staff Logic Design Engineer

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Devices Development Group Malaysia (DDG-MYS) Client SoC Team is seeking highly motivated engineering talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer.
In this role, you will contribute to Intel’s latest Client product families, helping build world-changing technology that reaches people around the globe.
Key Responsibilities Own DDG internal IP RTL design and development or integrate high-performance and high-bandwidth IP into Client SoC platforms.
Define, implement, and deliver new IP features, change requests, and feature enhancements.
Drive IP-to-SoC handoff quality, ensuring design completeness, compliance, and readiness for downstream integration.
Perform logic and RTL integration into SoC, including power intent definition, signal handling across power planes and clock domains, and delivery of front-end collateral for system and software integration.
Develop design solutions and collaborate closely with verification teams to validate functionality, features, and integration readiness.
Execute front-end quality checks across RTL static analysis, synthesizability, timing and power convergence, netlist quality, formal equivalence verification, and related design quality milestones.

Bachelor or Master Degree in Electrical and Electronic Engineering, Computer Engineering, Computer Science, or a related discipline, with at least 3 years of experience in IP or SoC RTL/Logic Design.
Strong knowledge of one or more of the following areas: IP/subsystem architecture, I/O architecture, and industry-standard high-speed bus protocols.
SoC/ASIC design methodology and industry-standard front-end development practices.
SoC fabric and interconnect design.
RTL design using Verilog and SystemVerilog.
Industry front-end and RTL tools, flows, and design methodologies.
Experience using AI tools or AI-assisted engineering workflows to improve RTL/Logic development productivity, including design exploration, code generation, review, debug, documentation, and front-end quality checks.
Ability to orchestrate efficient development workflows by combining domain expertise, automation, scripting, AI-assisted tools, and structured engineering practices to accelerate delivery while maintaining design quality.
Pre-silicon or post-silicon lab debug and power-on experience.
Excellent communication, collaboration, problem-solving, and teamwork skills.

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