SoC Design Engineering Manager

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About This Role

  • Intel Central Engineering Group is seeking SoC Design Engineering Manager to join our dynamic team and contribute to the development of cutting-edge custom IP and SoC designs for Intel products and Intel Custom ASIC Customers.
  • In this role, you will play a pivotal part in translating RTL to GDS, enabling manufacturing-ready design databases that drive innovation in products.
  • Leads and manages silicon design teams that span across more than one area of functional development including logic design, verification, circuit design, and/or physical design for an IP, subsystem, SoC, and/or discrete chip.
  • Manages the engineering team resources, their functions, activities, responsibilities, and driving continuous improvement and silicon quality standards.
  • Conducts design reviews to ensure key factors such as power, performance, area, and cost are meeting requirements.
  • Works to continuously to improve silicon development processes and architecture definition across areas of silicon design.
  • Oversees and reviews design verification test results, data analysis, issue tracking, root cause analysis, and drives corrective actions implementation for silicon design.
  • Works closely across IP and SoC development teams to design complex projects, ensure quality, drive performance, and design implementation.
  • Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
  • Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 18+ Years of experience in Physical Design execution. - Excellent track record in managing large physical design teams and delivering to multiple SoC tapeout on advanced technology nodes. - Deep knowledge in RTL-to-GDS workflows, including synthesis, place and route, and static timing analysis. - Track record of building large SOC design teams and demonstrating engineering excellence in physical design execution. - Demonstrated ability to collaborate across cross functional spanning across geos to achieve the tapeout goals. - Strong critical thinking and problem-solving skills to manage complex design challenges. - Excellent communication and organizational abilities to coordinate across disciplines. - A passion for innovation and continuous improvement in design execution and KPIs.

Sourced directly from Intel’s career page

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Intel

India, Bangalore

Specialisation
Salary range
₹6-14 LPA to ₹45-80 LPA
Open roles at Intel
624 positions
Job ID
/job/India-Bangalore/SoC-Design-Engineering-Manager_JR0285862

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