Opens intel.wd1.myworkdayjobs.com in a new tab
About This Role
- This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.
- Join a highly skilled silicon debug solution organization responsible for developing, maintaining, and supporting a proprietary JTAG-based debug tool used across a major high tech hardware company.
- Our tool is integral to bringing up, validating, and debugging cutting-edge microprocessors and SoCs.
- We serve pre- and post-silicon, validation and debug teams worldwide.
- Position Overview We are seeking an early-career FPGA Developer interested in RTL design and verification (VHDL/Verilog/SystemVerilog).
- In this role, you will contribute to FPGA-based features that support and extend our proprietary JTAG-based debug tool.
- You'll work with experienced engineers who will provide mentorship as you learn our architecture, development flow, and lab bring-up practices.
- This is an opportunity to grow your FPGA skills at the intersection of silicon validation and debug technology while delivering improvements that help teams debug and validate cutting-edge microprocessors and SoCs.
- Key Responsibilities Implement and maintain FPGA RTL (VHDL/Verilog/SystemVerilog) under guidance to enable and enhance debug/validation capabilities.
- Assist with integrating FPGA designs with JTAG/TAP interfaces and debug transport/control logic.
- Write and run simulations; help develop testbenches and automated checks to validate functional correctness.
- Debug RTL and hardware issues using waveforms, assertions, and on-hardware instrumentation (e.g., ILA/SignalTap) with support from the team.
- Contribute to FPGA build flows (synthesis/place-and-route/bitstream) and help improve reproducibility and resource utilization.
- Collaborate with software, validation, and hardware teams to clarify requirements, implement changes, and support internal users.
- Behavioral traits Foundational debug skills and a willingness to learn: willingness to investigate issues using simulation, waveforms, and structured troubleshooting.
- Communication skills and willingness to collaborate with cross-functional teams.
- Additional Opportunities Build FPGA-based test and demo environments to accelerate validation, debug, and internal enablement.
- Contribute to automation around FPGA builds, regression testing, and lab workflows (e.g., scripting, CI, environment setup).
- Why Join Us? Work on a proprietary debug tool used at massive scale across a world-class hardware organization.
- Solve complex, meaningful problems at the intersection of FPGA, software, and silicon validation.
- Influence infrastructure that directly impacts silicon bring up and validation velocity.
- Grow your skills alongside highly experienced engineers in a collaborative environment.
Requirements
- are required to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Requirements
- Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electronics Engineering, or a related field.
- A minimum of 2 years of experience is required for candidates with a Bachelor’s degree, while no prior experience is required for candidates with a Master’s degree.
- Experience mentioned above should be in the following areas: FPGA/RTL development (including internships, co-ops, or substantial academic/personal projects).
- VHDL and/or Verilog/SystemVerilog (ability to read, modify, and write RTL).
- Advance English level.
- Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).
Nice to Have
- Git and basic software development practices (branching, reviews, documentation).
- Exposure to FPGA vendor toolchains (e.g., Xilinx Vivado, Intel Quartus) and constraints (XDC/SDC).
- Exposure to RTL verification concepts (testbenches, assertions/SVA; UVM familiarity is a plus).
- Familiarity with JTAG/TAP, boundary scan, and debug/bring-up flows.
- Experience debugging FPGA designs in hardware (e.g., ILA/SignalTap) is a plus.
- Basic scripting (Python/Tcl/Bash) for automation and tooling integration is a plus.
- Interest or exposure to CI/regression practices for hardware/FPGA flows is a plus.
- Understanding of clock-domain crossing, reset strategy, and timing/performance tradeoffs is a plus.
- Familiarity with common interfaces (e.g., AXI, PCIe, Ethernet) is a plus.
- Interest in lab bring-up/validation and working with hardware teams.
- If you are passionate about innovation, thrive in collaborative environments, and seek to make a meaningful impact on the future of technology, we encourage you to apply today.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
Opens intel.wd1.myworkdayjobs.com in a new tab
Specialisation
Salary range
₹6-14 LPA to ₹45-80 LPA
Open roles at Intel
765 positions
Job ID
/job/Mexico-Guadalajara/SoC-Debug-Engineer_JR0283572
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — free
