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About This Role
- Drives end-to-end development for silicon packaging substrate design from concept through tapeout and implements physical layout and routing of the package design.
- Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs.
- Works closely with silicon and hardware teams to optimize silicon package board performance and pinout.
- Utilizes and defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves design rules violations to optimize package design.
- Completes documentation and collaterals into the product lifecycle management system of record.
- Communicates and responds to customer requests and participates in customer engaging events as they occur.
- Provides consultation concerning packaging problems and improvements in the packaging process.
- Key Responsibilities: - Perform substrate fit and routing studies to assess design, performance, and cost tradeoffs. - Implement physical layout and routing of package designs, ensuring adherence to design rules. - Optimize silicon-package-board performance and pinout by working closely with silicon and hardware teams. - Define substrate design rules and conduct internal and external design reviews. - Analyze data and resolve design rule checks (DRCs) to refine package designs. - Drive design-for-manufacturability (DFM) strategies to enhance manufacturability and cost efficiency. - Develop comprehensive documentation and collateral, storing them in the product lifecycle management system of record. - Team player with experience collaborating with customers - Communication and stakeholder management skills Qualifications: Minimum Qualifications Bachelor’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or Physics with 4+ years of experience.
- Or Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or Physics with 3+ years of experience.
- Or Phd degree in Electrical Engineering, Mechanical Engineering, Materials Science, or Physics.
- Experience listed above should be a combination of the following: Package or board design and review tools like Siemens Xpedition, Cadence Allegro Package Design, Valor NPI, AutoCAD, or SolidWorks.
- Expertise in Package Design and Development, interconnect methodologies, and/or manufacturability principles.
- Package Fundamentals.
Nice to Have
- Demonstrated ability to collaborate with cross-functional teams and optimize design tradeoffs. - Exceptional analytical skills and a detail-oriented approach to problem-solving. - Prior experience with substrate design rules and DRC resolution. - Excellent communication and documentation skills to manage complex data and technical reviews. - Familiarity with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS. - Strong analytical ability and problem-solving skills, including debugging and providing creative solutions. - Experience with scripting using Python, VB, C, or similar languages.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Sourced directly from Intel’s career page
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Specialisation
Open roles at Intel
765 positions
Job ID
/job/US-Arizona-Phoenix/Silicon-Packaging-Design-Engineer_JR0283552
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