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About This Role
- The Role and Impact We are seeking a Silicon Packaging Design Architect to join our team, where you will drive end-to-end package solutions for physical, electrical, and cost requirements.
- In this senior engineering role, you will collaborate with cross-functional teams to design, troubleshoot, and continuously improve packaging standards and processes, ensuring high-quality package output.
- Your contributions will directly impact the seamless transition of designs to production and enhance Intel's advanced packaging technologies.
- Business Group As part of Intel Corporation's dynamic and innovative ecosystem, this role resides within the Silicon Packaging Architecture team, focused on developing advanced packaging solutions that enable Intel's cutting-edge silicon technologies.
- The team plays a vital role in ensuring packaging, and 3D IC designs meet technical, mechanical, and reliability standards while supporting Intel's broader mission to drive world-changing advancements in technology.
- Key Responsibilities Translate product requirements into detailed package architecture specifications.
- Drive technology tradeoff decisions to ensure silicon packages conform to electrical, mechanical, thermal, and reliability standards.
- Collaborate with silicon, hardware, and package teams to deliver high-quality package solutions and overcome roadblocks.
- Oversee the end-to-end package development process, including design, procedures, and continuous improvements to quality standards.
- Troubleshoot packaging designs and resolve issues related to materials and processes, providing innovative and cost-effective solutions.
- Implement co-design strategies between silicon and board design teams to optimize product performance and cost.
- Collaborate with EDA partners to advance package design tools and optimize design methods.
- Core Competencies Strong analytical, communication, and organizational skills.
- Proven ability to manage multiple priorities and deadlines in a dynamic environment.
Requirements
- are required to be initially considered for this position.
- Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research.
- The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Minimum Qualifications US Citizenship required.
- Ability to obtain and maintain US Government TS/SCI Security Clearance with Polygraph.
- Option 1: Bachelor's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 6+ years of experience.
- Option 2: Master's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 4+ years of experience.
- Option 3: Ph.D. in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 2+ years of experience. 2+ years of hands-on experience in semiconductor fabrication, chip assembly, or packaging.
- Experience in electromagnetic simulation tools such as Mentor, Cadence tools, SPICE, Ansys tools, or similar platforms.
- Experience with Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity) and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).
- In-depth knowledge of assembly processes, test methodologies, and characterization techniques.
- Preferred Qualifications Active US Government TS/SCI Security Clearance with Polygraph. 10+ years of experience with profound knowledge in Package, PCB design, or IC digital design.
- Experience in troubleshooting and optimizing packaging designs for cost and quality.
- Strong analytical and problem-solving skills, including the ability to identify, isolate, and resolve complex design issues.
- Experience in semiconductor fabrication and packaging processes.
- Experience collaborating with multidisciplinary teams across various levels of abstraction.
- Experience with technology trade-off decisions to ensure high-quality package outputs.
- We look forward to welcoming innovative thinkers who are passionate about shaping the future of technology.
- Apply today to make an impact and join Intel's journey toward groundbreaking advancements.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Tools & Skills
Sourced directly from Intel’s career page
Your application goes straight to Intel.
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Specialisation
Open roles at Intel
666 positions
Job ID
/job/US-Arizona-Phoenix/Silicon-Packaging-Design-Architect_JR0287863
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