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About This Role
- Shape the Future of Computing at Intel Intel is seeking an experienced Senior Static Timing Analysis (STA) Engineer to help drive the development of next-generation semiconductor products.
- In this role, you will play a critical part in delivering high-performance, power-efficient System-on-Chip (SoC) designs that power industry-leading technologies.
- You will work across architecture, logic design, clocking, DFT, and physical design teams to ensure successful timing convergence, signal integrity, performance optimization, and product readiness.
- This position offers an exciting opportunity to solve complex engineering challenges while influencing methodologies and best practices used across advanced SoC programs.
- Key Responsibilities but not limited to: Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
- Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
- Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
- Define methodologies to produce high-quality timing models and enable efficient physical design execution.
- Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
- Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
- Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
- Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.
- Behavioral Traits We Are Looking For Technical Leadership: Demonstrates strong engineering judgment and influences technical direction across complex projects.
- Ownership and Accountability: Takes responsibility for challenging technical problems and drives them to closure.
- Strategic Problem Solving: Applies analytical thinking and data-driven decision-making to solve highly complex design challenges.
- Cross-Functional Collaboration: Builds trusted partnerships across architecture, design, validation, DFT, clocking, and physical design teams.
- Communication Excellence: Communicates complex technical concepts effectively to technical and non-technical audiences.
- Continuous Improvement Mindset: Identifies opportunities to improve methodologies, tools, and engineering efficiency.
- Mentorship: Shares knowledge, coaches peers, and contributes to the development of engineering talent.
- Adaptability: Thrives in fast-paced environments with evolving priorities and technical challenges.
- Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
- See Intel Benefits for more details.
Requirements
- to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S.
- Immigration Sponsorship Information Minimum Qualifications and Experience: Bachelor's degree in Computer Engineering, Computer Science, or related STEM discipline and 6+ years of industry experience; OR a Master's degree in the same fields and 4+ years of experience. 5+ years of experience the following: SOC level static timing analysis, clock network design, and timing closure methodologies.
- Timing constraint adaptation, physical design knowledge, and optimization techniques.
- Industry-standard tools for timing analysis, extraction, and physical design.
- TCL scripting and timing budgeting processes.
- Preferred Skills/Experience: A PhD in the same filed and 2+ years of experience.
- Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
- Knowledge of tools, flows, and methodologies for high-performance physical design.
- Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
- DFT architecture knowledge is a strong plus.
- Why Join Intel Join Intel and play a key role in delivering next-generation SoC products that power future computing innovations.
- You will work across global teams, influence high-impact design decisions, collaborate with leading engineers, and help drive technologies from development through product delivery.
- This is an opportunity to solve complex technical challenges while contributing to Intel's expanding product roadmap and future growth.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
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/job/US-Arizona-Phoenix/Senior-Static-Timing-Analysis--STA--Engineer_JR0286869-1
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