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About This Role
- About the Role The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon.
- Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency.
- We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.
- We are seeking a Senior SoC Network Subsystem Architect to define and lead the architecture of high-performance network subsystems for next-generation IPU/DPU platforms.
- This role focuses on designing scalable, programmable networking pipelines that support hyperscale and cloud data center workloads.
- You will drive the end-to-end Network Subsystem (NSS) architecture , including packet processing pipelines, protocol engines, QoS frameworks, and observability features.
- This is a highly cross-functional leadership role requiring deep technical expertise and strong collaboration across hardware, software, and systems teams.
- What You’ll Do Key responsibilities will include but not limited to: Network Subsystem Architecture Definition 1.
- Own end-to-end NSS architecture, including packet processing pipelines, protocol engines, and interface datapaths 2.
- Architect high-performance packet pipelines supporting hundreds of millions of packets/sec throughput and processing flows 3.
- Drive architectural direction for programmable vs. fixed-function pipeline balance and future extensibility 4.
- Specify network subsystem pipeline scaling strategies and define multi-generation NSS architecture roadmap 6.
- Lead design decisions for pipeline partitioning, feature scalability, and backward compatibility QoS, Scheduling, and Flow Management 1.
- Architect advanced scheduling frameworks (per-flow shaping, multi-level scheduling, traffic class isolation) 2.
- Define QoS models to support multi-tenant workloads, virtualization, and service chaining Debug, Telemetry, and Observability 1.
- Define architecture for telemetry, performance counters, and real-time observability of pipeline behavior 2.
- Architecture support for field debug, failure triage, and large-scale deployment monitoring Cross-Functional Leadership 1.
- Collaborate across SoC, compute, memory, SW/FW, validation, and customer teams to drive architecture closure 2.
- Interface with external customers to translate workload requirements into NSS architecture decisions 3.
- Lead architectural reviews and influence cross-team technical direction Behavioral traits that we are looking for: Strategic thinker: Ability to define long-term architecture vision and align stakeholders Technical leadership: Influences across teams without direct authority Problem solver: Approaches complex system challenges with structured thinking Collaboration: Builds strong partnerships across engineering disciplines Customer-focused mindset: Translates real-world workload needs into solutions Adaptability: Navigates ambiguity and evolving technical requirements Ownership mindset: Drives initiatives from concept through execution Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
- See Intel Benefits for more details.
Requirements
- are required to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S.
- Immigration Sponsorship Information Minimum Qualifications and Experience : Bachelor’s degree in Electrical/Computer Engineering, Computer Science or related degree with 7 + years of experience.
- You must have 7+ years of experience in the following: Networking ASIC / SoC / IPU / DPU architecture High-speed packet processing pipelines Experience in system-level architecture tradeoffs Define and deliver architecture for large-scale data center networking systems Preferred Qualifications and Experience : Experience with programmable datapath architectures (P4, pipeline microcode, or hybrid models) Experience with AI/HPC scale-out networking and congestion control architectures Transport protocols offloads QoS, scheduling, and multi-tenant isolation Familiarity with coherent or shared-memory offload models (e.g., CPU-IPU integration) Experience with hyperscaler deployments or customer co-design engagements Join us in building a brighter future through technology innovation! Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, California, San Jose, US, Oregon, Hillsboro, US, Texas, Austin Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).
- The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
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₹6-14 LPA to ₹45-80 LPA
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/job/US-California-Santa-Clara/Senior-SoC-Network-Subsystem-Architect_JR0284568
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