Senior Signal Integrity Engineer (Hands-on)

About This Role

• Intel Central Engineering Group (CEG) team delivers best-in-class Ethernet products and is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing devices.
• CEG's compelling Ethernet products move the world's data and are the foundations of cloud service and telecommunications data centers.
• You will be exposed to High-Speed I/O protocols such as PCIeGen6-7, DDR5-6, and PAM4 Ethernet 224Gb, which are a part of our Ethernet Infrastructure Processing Unit (Intel IPU) and Foundation NIC (FNIC) Ethernet product lines.
• We propose a dynamic and flexible workplace position, working directly with highly capable design, system, and pre/post-silicon teams within the organization.
• Most of the team's engineers have 10+ years of experience, and we are looking for a highly skilled multidisciplinary engineer with proven experience in Signal Integrity engineering to lead the hardware design of our next division projects' challenges and be part of Ethernet networking's accelerated growth.
• In this position, as a signal integrity engineer, you will be responsible for modeling channel elements in 3D and 2D EM simulation tools for pre- and post-layout stages of package and platform design for PCIe, Ethernet, and memory interfaces.
• You are expected to have a thorough understanding of RF circuits and electromagnetic wave propagation; the role includes learning the specifications of each interface and the required design limitations that should be verified.
• You will be expected to lead all signal integrity activities related to multiple projects for various high-speed and low-speed interfaces utilizing traditional and automated tools.
• You will work closely with silicon design teams and Hard IP vendors and will be responsible for the model's correlation based on cross-section and electrical measurements at the post-manufacturing stage and modeling manufacturing variation impact on the channels.
• You will be responsible for running the sign-off simulation flows for various designs, providing feedback to the design teams, and being hands-on in the lab for experiments when required.
• You would also be responsible for identifying/qualifying new AI-based automation techniques and solutions and providing technical leadership to working groups/task forces through debugging and reviews.