Senior IP Architect – Unified Intel Chassis (UIC) IP and Platform Architecture

About This Role

• Role Overview: We are looking for an architecture lead to define and drive architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems.
• This role combines architecture definition with implementation awareness and performance ownership.
• The candidate will work on platform-level performance, including building performance environments and driving closure in partnership with system architects and cross-functional teams.
• Definition of platforms- From IP level performance modelling platforms (like modelling a routing algorithm, an arbiter policy et al) Then scaled to larger subsystem/soc level performance modelling platforms (like full soc network modelling) The performance evaluation setups must feed into architectural decisions driving scalable and performant design components.
• Key Responsibilities: - Author architecture specifications for Unified Intel Chassis IP components and subsystem integration. - Ensure architecture is implementation-aware, scalable, and power-optimized. - Drive platform performance analysis and closure, including bottleneck identification and optimization. - Build and enhance platform performance environments, models, and benchmarking flows. - Define and validate end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic. - Partner with system architects, RTL/design, verification, firmware/software, and performance teams to align architecture with product goals. - Define architecture trade-offs, assumptions, interfaces, and measurable success criteria.
• UIC IP Scope: - UIC Coherent and Non-Coherent Fabric - Protocol Adaptors for industry-standard protocols (AXI, CHI, CXL, UAL, etc.) - Cache Controller IP - MMU / IOMMU IP - Clock, Reset, and Power Management IP - Debug and Analytics IP - Security and Access Management IP Qualifications: Required Qualifications: - MS degree in a specialized field such as Computer Science, Electrical Engineering, or related discipline along with 4 or more years of relevant technical experience. - Strong experience in SoC IP architecture for complex interconnect and subsystem design. - familiarity with AMBA protocols, especially AXI, CHI, and APB. - Experience arbitration and routing algorithms, end-to-end QoS, and high-bandwidth low latency, scalable designs. - Hands-on experience with building platform environments which can be scaled to model small IP components to complete network model - Ability to define architecture requirements, interface contracts, performance targets, and power/performance/area trade-offs. - familiarly with AI tools to develop machine readable specification documents for spec2silicon fast and reliable execution - Strong collaboration and communication skills across architecture and implementation teams.